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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id kv18-20020a17090778d200b00a1dfc541282sm8048914ejc.225.2023.12.13.08.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 08:25:39 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/4] arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes Date: Wed, 13 Dec 2023 17:25:32 +0100 Message-Id: <20231213162536.171475-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 13 Dec 2023 08:25:46 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785184652460601823 X-GMAIL-MSGID: 1785184652460601823 Pin configuration for Soundwire bus should be set in Soundwire controller nodes, not in the associated macro codec node. This placement change should not have big impact in general, because macro codec is a clock provider for Soundwire controller, thus its devices is probed first. However it will have impact for disabled Soundwire buses, e.g. WSA2, because after this change the pins will be left in default state. We also follow similar approach in newer SoCs, like Qualcomm SM8650. Signed-off-by: Krzysztof Kozlowski Acked-by: Konrad Dybcio --- Not tested on HW. --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 12e55a0c7417..3b6ea9653d2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2160,8 +2160,6 @@ wsa2macro: codec@31e0000 { #clock-cells = <0>; clock-output-names = "wsa2-mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa2_swr_active>; #sound-dai-cells = <1>; }; @@ -2173,6 +2171,9 @@ swr4: soundwire-controller@31f0000 { clock-names = "iface"; label = "WSA2"; + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <2>; qcom,dout-ports = <6>; @@ -2208,8 +2209,6 @@ rxmacro: codec@3200000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&rx_swr_active>; #sound-dai-cells = <1>; }; @@ -2223,6 +2222,9 @@ swr1: soundwire-controller@3210000 { qcom,din-ports = <0>; qcom,dout-ports = <5>; + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; @@ -2254,8 +2256,6 @@ txmacro: codec@3220000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&tx_swr_active>; #sound-dai-cells = <1>; }; @@ -2275,8 +2275,6 @@ wsamacro: codec@3240000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa_swr_active>; #sound-dai-cells = <1>; }; @@ -2288,6 +2286,9 @@ swr0: soundwire-controller@3250000 { clock-names = "iface"; label = "WSA"; + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <2>; qcom,dout-ports = <6>; @@ -2318,6 +2319,9 @@ swr2: soundwire-controller@33b0000 { clock-names = "iface"; label = "TX"; + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <0>; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;