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[6/9] dt-bindings: riscv: add Zacas ISA extension description

Message ID 20231213113308.133176-7-cleger@rivosinc.com
State New
Headers
Series riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support |

Commit Message

Clément Léger Dec. 13, 2023, 11:33 a.m. UTC 
  Add description for the Zacas ISA extension which was ratified recently.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Conor Dooley Dec. 14, 2023, 2:12 p.m. UTC | #1 
On Wed, Dec 13, 2023 at 12:33:02PM +0100, Clément Léger wrote:
> Add description for the Zacas ISA extension which was ratified recently.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 912cc6a42eb4..264114fa943e 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -171,6 +171,12 @@  properties:
             memory types as ratified in the 20191213 version of the privileged
             ISA specification.
 
+        - const: zacas
+          description: |
+            The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
+            is supported as ratified at commit 5059e0ca641c ("update to
+            ratified") of the riscv-zacas.
+
         - const: zam
           description: |
             The standard Zam extension for misaligned atomics is supported as