diff mbox series

[3/9] dt-bindings: riscv: add Zam ISA extension description

Message ID	20231213113308.133176-4-cleger@rivosinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Jonathan Corbet <corbet@lwn.net>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Robbin Ehn <rehn@rivosinc.com> Subject: [PATCH 3/9] dt-bindings: riscv: add Zam ISA extension description Date: Wed, 13 Dec 2023 12:32:59 +0100 Message-ID: <20231213113308.133176-4-cleger@rivosinc.com> In-Reply-To: <20231213113308.133176-1-cleger@rivosinc.com> References: <20231213113308.133176-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support \| [0/9] riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support [1/9] riscv: add ISA extension parsing for Ztso [2/9] riscv: hwprobe: export Ztso ISA extension [3/9] dt-bindings: riscv: add Zam ISA extension description [4/9] riscv: add ISA extension parsing for Zam [5/9] riscv: hwprobe: export Zam ISA extension [6/9] dt-bindings: riscv: add Zacas ISA extension description [7/9] riscv: add ISA extension parsing for Zacas [8/9] riscv: hwprobe: export Zacas ISA extension [9/9] riscv: hwprobe: export Zicond extension

Commit Message

Clément Léger Dec. 13, 2023, 11:32 a.m. UTC

  Add description for the Zam ISA extension.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Conor Dooley Dec. 14, 2023, 2:11 p.m. UTC | #1

On Wed, Dec 13, 2023 at 12:32:59PM +0100, Clément Léger wrote:
> Add description for the Zam ISA extension.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
>  Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 3574a0b70be4..912cc6a42eb4 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -171,6 +171,11 @@ properties:
>              memory types as ratified in the 20191213 version of the privileged
>              ISA specification.
>  
> +        - const: zam
> +          description: |
> +            The standard Zam extension for misaligned atomics is supported as
> +            ratified in version 20191213 of the riscv-isa-manual.

Is "20191213" an actual tag in that repo? Looking at that version of the
spec (because it is a spec version, but I don't think it is a valid
reference to that repo) Zam is listed as Draft. In fact, in the most
recent thing I could find, Zam was still listed as draft.

Are you sure this is ratified?

Clément Léger Dec. 15, 2023, 8:26 a.m. UTC | #2

On 14/12/2023 15:11, Conor Dooley wrote:
> On Wed, Dec 13, 2023 at 12:32:59PM +0100, Clément Léger wrote:
>> Add description for the Zam ISA extension.
>>
>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>> ---
>>  Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> index 3574a0b70be4..912cc6a42eb4 100644
>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> @@ -171,6 +171,11 @@ properties:
>>              memory types as ratified in the 20191213 version of the privileged
>>              ISA specification.
>>  
>> +        - const: zam
>> +          description: |
>> +            The standard Zam extension for misaligned atomics is supported as
>> +            ratified in version 20191213 of the riscv-isa-manual.
> 
> Is "20191213" an actual tag in that repo? Looking at that version of the
> spec (because it is a spec version, but I don't think it is a valid
> reference to that repo) Zam is listed as Draft. In fact, in the most
> recent thing I could find, Zam was still listed as draft.

Whoops, my bad, I assumed that the chapter being present in the spec
meant it was ratified and I did not checked the listing stating it is
still in draft.

Will remove that from the next version.

Thanks,

Clément

> 
> Are you sure this is ratified?

diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 3574a0b70be4..912cc6a42eb4 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -171,6 +171,11 @@  properties:
             memory types as ratified in the 20191213 version of the privileged
             ISA specification.
 
+        - const: zam
+          description: |
+            The standard Zam extension for misaligned atomics is supported as
+            ratified in version 20191213 of the riscv-isa-manual.
+
         - const: zba
           description: |
             The standard Zba bit-manipulation extension for address generation