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Mon, 11 Dec 2023 16:53:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Dec 2023 16:53:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Dec 2023 16:53:06 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Marc Zyngier CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH v2 1/3] PCI: mediatek: Allocate MSI address with dmam_alloc_coherent() Date: Mon, 11 Dec 2023 16:52:54 +0800 Message-ID: <20231211085256.31292-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211085256.31292-1-jianjun.wang@mediatek.com> References: <20231211085256.31292-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.452000-8.000000 X-TMASE-MatchedRID: YlUeb+P3LGlBHBd/Q+ztBwPZZctd3P4BIaVkFIrQFhtb6PBUqmq+UlYu mEk/UtlHxvP5MvmYpyBTc0C6OSQvz8pFJHzzp4rS58dk5sbwmyjGYnoF/CTeZVSOymiJfTYXlwW f7/4SyDtrg8FCypqvfGmevJVqJe6AHxPMjOKY7A8LbigRnpKlKZvjAepGmdoOjSE7r38ccucfAi JtYJYn7WCx0B/Tk9JmY616mIENddzqpQj72dAQYgHduAz87L4zdUVIHoasg2idNYuO1rAFqL0we Uq5YYes8jae4OD13tAV7Mc+rowcVKtX/F0pBwVJjSV5hDFby7ZnIxZyJs78kg== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.452000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3399B1CCA37B4999E57B22197D5592ECC7DE562E04091DEA609953BF1EF284B22000:8 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 11 Dec 2023 00:53:35 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784974996627304757 X-GMAIL-MSGID: 1784975003096113812 Use dmam_alloc_coherent() to allocate the MSI address, instead of using virt_to_phys(). Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 66a8f73296fc..2fb9e44369f8 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -178,6 +178,7 @@ struct mtk_pcie_soc { * @phy: pointer to PHY control block * @slot: port slot * @irq: GIC irq + * @msg_addr: MSI message address * @irq_domain: legacy INTx IRQ domain * @inner_domain: inner IRQ domain * @msi_domain: MSI IRQ domain @@ -198,6 +199,7 @@ struct mtk_pcie_port { struct phy *phy; u32 slot; int irq; + dma_addr_t msg_addr; struct irq_domain *irq_domain; struct irq_domain *inner_domain; struct irq_domain *msi_domain; @@ -394,12 +396,10 @@ static struct pci_ops mtk_pcie_ops_v2 = { static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); - phys_addr_t addr; /* MT2712/MT7622 only support 32-bit MSI addresses */ - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); msg->address_hi = 0; - msg->address_lo = lower_32_bits(addr); + msg->address_lo = lower_32_bits(port->msg_addr); msg->data = data->hwirq; @@ -494,6 +494,14 @@ static struct msi_domain_info mtk_msi_domain_info = { static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) { struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); + void *msi_vaddr; + + msi_vaddr = dmam_alloc_coherent(port->pcie->dev, sizeof(dma_addr_t), &port->msg_addr, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(port->pcie->dev, "failed to alloc and map MSI address\n"); + return -ENOMEM; + } mutex_init(&port->lock); @@ -501,6 +509,7 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) &msi_domain_ops, port); if (!port->inner_domain) { dev_err(port->pcie->dev, "failed to create IRQ domain\n"); + dmam_free_coherent(port->pcie->dev, sizeof(dma_addr_t), msi_vaddr, port->msg_addr); return -ENOMEM; } @@ -508,6 +517,7 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) port->inner_domain); if (!port->msi_domain) { dev_err(port->pcie->dev, "failed to create MSI domain\n"); + dmam_free_coherent(port->pcie->dev, sizeof(dma_addr_t), msi_vaddr, port->msg_addr); irq_domain_remove(port->inner_domain); return -ENOMEM; } @@ -518,10 +528,8 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) { u32 val; - phys_addr_t msg_addr; - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); - val = lower_32_bits(msg_addr); + val = lower_32_bits(port->msg_addr); writel(val, port->base + PCIE_IMSI_ADDR); val = readl(port->base + PCIE_INT_MASK); @@ -588,7 +596,7 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, if (IS_ENABLED(CONFIG_PCI_MSI)) { ret = mtk_pcie_allocate_msi_domains(port); if (ret) - return ret; + dev_warn(dev, "no MSI supported, only INTx available\n"); } return 0; @@ -732,7 +740,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val &= ~INTX_MASK; writel(val, port->base + PCIE_INT_MASK); - if (IS_ENABLED(CONFIG_PCI_MSI)) + if (IS_ENABLED(CONFIG_PCI_MSI) && port->msi_domain) mtk_pcie_enable_msi(port); /* Set AHB to PCIe translation windows */