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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id bq4-20020a056a02044400b005c685a2d34esi5798519pgb.321.2023.12.06.03.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:53:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id A891B81ADCDD; Wed, 6 Dec 2023 03:53:22 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378101AbjLFLxM convert rfc822-to-8bit (ORCPT + 99 others); Wed, 6 Dec 2023 06:53:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378213AbjLFLwu (ORCPT ); Wed, 6 Dec 2023 06:52:50 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E98D119AD; Wed, 6 Dec 2023 03:52:14 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6CC2B24E308; Wed, 6 Dec 2023 19:52:13 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:52:13 +0800 Received: from jsia-virtual-machine.localdomain (175.136.135.142) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 19:52:06 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , , Joshua Yeong Subject: [PATCH v1 15/16] reset: starfive: Add StarFive JH8100 reset driver Date: Wed, 6 Dec 2023 19:49:59 +0800 Message-ID: <20231206115000.295825-16-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> References: <20231206115000.295825-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [175.136.135.142] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:53:23 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784533340496646658 X-GMAIL-MSGID: 1784533340496646658 Add auxiliary reset driver to support StarFive JH8100 SoC. Co-developed-by: Joshua Yeong Signed-off-by: Joshua Yeong Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- MAINTAINERS | 7 ++ drivers/reset/starfive/Kconfig | 8 ++ drivers/reset/starfive/Makefile | 2 + .../reset/starfive/reset-starfive-jh8100.c | 102 ++++++++++++++++++ 4 files changed, 119 insertions(+) create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c diff --git a/MAINTAINERS b/MAINTAINERS index 87bcb25becc1..ed728f013d32 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20771,6 +20771,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml F: drivers/clk/starfive/jh8100 F: include/dt-bindings/clock/starfive?jh81*.h +STARFIVE JH8100 RESET CONTROLLER DRIVERS +M: Sia Jee Heng +M: Ley Foon Tan +S: Maintained +F: drivers/reset/starfive/reset-starfive-jh81* +F: include/dt-bindings/reset/starfive?jh81*.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig index 29fbcf1a7d83..88d050044d52 100644 --- a/drivers/reset/starfive/Kconfig +++ b/drivers/reset/starfive/Kconfig @@ -19,3 +19,11 @@ config RESET_STARFIVE_JH7110 default ARCH_STARFIVE help This enables the reset controller driver for the StarFive JH7110 SoC. + +config RESET_STARFIVE_JH8100 + bool "StarFive JH8100 Reset Driver" + depends on AUXILIARY_BUS && CLK_STARFIVE_JH8100_SYS + select RESET_STARFIVE_COMMON + default ARCH_STARFIVE + help + This enables the reset controller driver for the StarFive JH8100 SoC. diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile index 582e4c160bd4..ede1fc1c9601 100644 --- a/drivers/reset/starfive/Makefile +++ b/drivers/reset/starfive/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o + +obj-$(CONFIG_RESET_STARFIVE_JH8100) += reset-starfive-jh8100.o diff --git a/drivers/reset/starfive/reset-starfive-jh8100.c b/drivers/reset/starfive/reset-starfive-jh8100.c new file mode 100644 index 000000000000..84f3781a22a5 --- /dev/null +++ b/drivers/reset/starfive/reset-starfive-jh8100.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Reset driver for the StarFive JH8100 SoC + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include + +#include "reset-starfive-common.h" + +struct jh8100_reset_info { + unsigned int nr_resets; + unsigned int assert_offset; + unsigned int status_offset; +}; + +static const struct jh8100_reset_info jh8100_sys_info = { + .nr_resets = SYSCRG_RESET_NR_RESETS, + .assert_offset = 0x1B4, + .status_offset = 0x1B8, +}; + +static const struct jh8100_reset_info jh8100_sys_nw_info = { + .nr_resets = SYSCRG_NW_RESET_NR_RESETS, + .assert_offset = 0xA4, + .status_offset = 0xA8, +}; + +static const struct jh8100_reset_info jh8100_sys_ne_info = { + .nr_resets = SYSCRG_NE_RESET_NR_RESETS, + .assert_offset = 0x2BC, + .status_offset = 0x2C4, +}; + +static const struct jh8100_reset_info jh8100_sys_sw_info = { + .nr_resets = SYSCRG_SW_RESET_NR_RESETS, + .assert_offset = 0x28, + .status_offset = 0x2C, +}; + +static const struct jh8100_reset_info jh8100_aon_info = { + .nr_resets = AONCRG_RESET_NR_RESETS, + .assert_offset = 0x104, + .status_offset = 0x108, +}; + +static int jh8100_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct jh8100_reset_info *info = (struct jh8100_reset_info *) + (id->driver_data); + struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev); + void __iomem *base = rdev->base; + + if (!info || !base) + return -ENODEV; + + return reset_starfive_register(&adev->dev, + adev->dev.parent->of_node, + base + info->assert_offset, + base + info->status_offset, NULL, + info->nr_resets, NULL); +} + +static const struct auxiliary_device_id jh8100_reset_ids[] = { + { + .name = "clk_sys.rst-sys", + .driver_data = (kernel_ulong_t)&jh8100_sys_info, + }, + { + .name = "clk_sys.rst-sys-nw", + .driver_data = (kernel_ulong_t)&jh8100_sys_nw_info, + }, + { + .name = "clk_sys.rst-sys-ne", + .driver_data = (kernel_ulong_t)&jh8100_sys_ne_info, + }, + { + .name = "clk_sys.rst-sys-sw", + .driver_data = (kernel_ulong_t)&jh8100_sys_sw_info, + }, + { + .name = "clk_sys.rst-aon", + .driver_data = (kernel_ulong_t)&jh8100_aon_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, jh8100_reset_ids); + +static struct auxiliary_driver jh8100_reset_driver = { + .probe = jh8100_reset_probe, + .id_table = jh8100_reset_ids, +}; +module_auxiliary_driver(jh8100_reset_driver); + +MODULE_AUTHOR("Joshua Yeong "); +MODULE_AUTHOR("Sia Jee Heng "); +MODULE_DESCRIPTION("StarFive JH8100 reset driver"); +MODULE_LICENSE("GPL");