Message ID | 20231206105839.25805-20-minda.chen@starfivetech.com |
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State | New |
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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id il6-20020a17090b164600b002747da1ef66si11470489pjb.53.2023.12.06.03.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id B26EC826E3B5; Wed, 6 Dec 2023 03:01:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378043AbjLFLA3 (ORCPT <rfc822;pusanteemu@gmail.com> + 99 others); Wed, 6 Dec 2023 06:00:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378039AbjLFK7f (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 6 Dec 2023 05:59:35 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C910D10F1; Wed, 6 Dec 2023 02:59:11 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id AFA7880ED; Wed, 6 Dec 2023 18:58:59 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:59 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:58 +0800 From: Minda Chen <minda.chen@starfivetech.com> To: Conor Dooley <conor@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>, Rob Herring <robh+dt@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Lorenzo Pieralisi <lpieralisi@kernel.org>, "Daire McNamara" <daire.mcnamara@microchip.com>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-pci@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de>, Mason Huo <mason.huo@starfivetech.com>, Leyfoon Tan <leyfoon.tan@starfivetech.com>, Kevin Xie <kevin.xie@starfivetech.com>, Minda Chen <minda.chen@starfivetech.com> Subject: [PATCH v12 19/21] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Date: Wed, 6 Dec 2023 18:58:37 +0800 Message-ID: <20231206105839.25805-20-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:01:14 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530077154387051 X-GMAIL-MSGID: 1784530077154387051 |
Series |
Refactoring Microchip PCIe driver and add StarFive PCIe
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Commit Message
Minda Chen
Dec. 6, 2023, 10:58 a.m. UTC
From: Kevin Xie <kevin.xie@starfivetech.com> Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum waiting time between exit from a conventional reset and sending the first configuration request to the device. As described in PCI base specification r6.0, section 6.6.1 <Conventional Reset>, there are two different use cases of the value: - "With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms following exit from a Conventional Reset before sending a Configuration Request to the device immediately below that Port." - "With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port." Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> --- drivers/pci/pci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..06f1f1eb878c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 <Conventional + * Reset>, there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump;