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Peter Anvin" , Tony Luck , Sohil Mehta , Yazen Ghannam , Arnd Bergmann , linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: [PATCH] x86/mce: Update references to the Intel SDM Date: Wed, 6 Dec 2023 01:38:46 +0000 Message-Id: <20231206013846.1859347-1-sohil.mehta@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 05 Dec 2023 17:40:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784494809395298415 X-GMAIL-MSGID: 1784494809395298415 Chapter numbers in the SDM are not expected to be stable. In case of Machine-Check Architecture, it has moved from chapter 15 to chapter 16 with the recent SDM updates. Instead of changing the chapter number and having to do it again later, update the comments with 'Chapter name -> "Sub-section name"' to keep it easy enough to find the specific reference. Note, this intentionally skips the intermediate section names to avoid making the comments unnecessarily wordy. Signed-off-by: Sohil Mehta --- There are other places in arch/x86 that have stale references to the SDM as well. I am sending an MCE specific patch first to get a pulse. I can send out more patches if this approach seems reasonable. I am open to suggestions, is there a better way to do this? Or should we get rid of the references all together (expect for really the obscure text that would be hard to find otherwise)? --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/core.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6de6e1d95952..35fa25eb815b 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -72,7 +72,7 @@ */ #define MCACOD 0xefff /* MCA Error Code */ -/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ +/* Architecturally defined error codes from SDM: Machine-Check Architecture */ #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7b397370b4d6..d42122b1afea 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -482,7 +482,8 @@ bool mce_is_memory_error(struct mce *m) case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: /* - * Intel SDM Volume 3B - 15.9.2 Compound Error Codes + * Intel SDM: Machine-Check Architecture -> "Compound Error + * Codes" * * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for * indicating a memory error. Bit 8 is used for indicating a @@ -698,7 +699,8 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) goto log_it; /* - * Log UCNA (SDM: 15.6.3 "UCR Error Classification") + * Log UCNA (Intel SDM: Machine-Check Architecture -> "UCR + * Error Classification") * UC == 1 && PCC == 0 && S == 0 */ if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))