Message ID | 20231205173252.62305-1-imbrenda@linux.ibm.com |
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Tue, 5 Dec 2023 17:32:52 +0000 (GMT) From: Claudio Imbrenda <imbrenda@linux.ibm.com> To: linux-kernel@vger.kernel.org Cc: linux-s390@vger.kernel.org, linux390-list@tuxmaker.boeblingen.de.ibm.com, kvm390-list@tuxmaker.boeblingen.de.ibm.com, hca@linux.ibm.com, borntraeger@de.ibm.com, frankja@linux.ibm.com, nrb@linux.ibm.com, nsg@linux.ibm.com, svens@linux.ibm.com, gor@linux.ibm.com, gerald.schaefer@linux.ibm.com, agordeev@linux.ibm.com Subject: [PATCH v1 1/1] s390: mm: convert pgste locking functions to C Date: Tue, 5 Dec 2023 18:32:52 +0100 Message-ID: <20231205173252.62305-1-imbrenda@linux.ibm.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: BJkgwvXplodQTkKRLbAtdTM0yCZVkiXT X-Proofpoint-GUID: BJkgwvXplodQTkKRLbAtdTM0yCZVkiXT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-05_12,2023-12-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 mlxlogscore=373 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2312050139 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); 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Series |
[v1,1/1] s390: mm: convert pgste locking functions to C
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Commit Message
Claudio Imbrenda
Dec. 5, 2023, 5:32 p.m. UTC
Convert pgste_get_lock() and pgste_set_unlock() to C.
There is no real reasons to keep them in assembler. Having them in C
makes them more readable and maintainable, and better instructions are
used automatically when available.
Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
---
arch/s390/mm/pgtable.c | 29 ++++++++++-------------------
1 file changed, 10 insertions(+), 19 deletions(-)
Comments
On Tue, Dec 05, 2023 at 06:32:52PM +0100, Claudio Imbrenda wrote: > Convert pgste_get_lock() and pgste_set_unlock() to C. > > There is no real reasons to keep them in assembler. Having them in C > makes them more readable and maintainable, and better instructions are > used automatically when available. > > Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com> > --- > arch/s390/mm/pgtable.c | 29 ++++++++++------------------- > 1 file changed, 10 insertions(+), 19 deletions(-) Reviewed-by: Heiko Carstens <hca@linux.ibm.com>
On Tue, Dec 05, 2023 at 06:32:52PM +0100, Claudio Imbrenda wrote: Hi Claudio, > Convert pgste_get_lock() and pgste_set_unlock() to C. > > There is no real reasons to keep them in assembler. Having them in C > makes them more readable and maintainable, and better instructions are > used automatically when available. > > Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com> > --- > arch/s390/mm/pgtable.c | 29 ++++++++++------------------- > 1 file changed, 10 insertions(+), 19 deletions(-) Acked-by: Alexander Gordeev <agordeev@linux.ibm.com>
On Tue, Dec 05, 2023 at 06:32:52PM +0100, Claudio Imbrenda wrote: (Internal lists only) ... > + do { > + value = __atomic64_or_barrier(PGSTE_PCL_BIT, ptr); Would it make sense to cpu_relax() here, e.g with a follow-up patch? > + } while (value & PGSTE_PCL_BIT); > + value |= PGSTE_PCL_BIT; > #endif > - return __pgste(new); > + return __pgste(value); > } Thanks!
On Wed, Dec 06, 2023 at 10:01:18AM +0100, Alexander Gordeev wrote: > On Tue, Dec 05, 2023 at 06:32:52PM +0100, Claudio Imbrenda wrote: > ... > > + do { > > + value = __atomic64_or_barrier(PGSTE_PCL_BIT, ptr); > > Would it make sense to cpu_relax() here, e.g with a follow-up patch? No, because cpu_relax() is a no-op on our architecture (besides that it translates to barrier(); but __atomic64_or_barrier() obviously comes also with barrier() semantics). We used to do diag 0x44 with cpu_relax() but that caused many performance problems, therefore we removed diag 0x44 completely from the kernel quite some time ago. See also commit 1b68ac8678a8 ("s390: remove last diag 0x44 caller").
On Wed, Dec 06, 2023 at 10:15:41AM +0100, Heiko Carstens wrote: > On Wed, Dec 06, 2023 at 10:01:18AM +0100, Alexander Gordeev wrote: > > On Tue, Dec 05, 2023 at 06:32:52PM +0100, Claudio Imbrenda wrote: > > ... > > > + do { > > > + value = __atomic64_or_barrier(PGSTE_PCL_BIT, ptr); > > > > Would it make sense to cpu_relax() here, e.g with a follow-up patch? > > No, because cpu_relax() is a no-op on our architecture (besides that it > translates to barrier(); but __atomic64_or_barrier() obviously comes also > with barrier() semantics). > > We used to do diag 0x44 with cpu_relax() but that caused many performance > problems, therefore we removed diag 0x44 completely from the kernel quite > some time ago. > > See also commit 1b68ac8678a8 ("s390: remove last diag 0x44 caller"). Thanks for the clarification! Applied.
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 3bd2ab2a9a34..6c4523aa4fdf 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -125,32 +125,23 @@ static inline pte_t ptep_flush_lazy(struct mm_struct *mm, static inline pgste_t pgste_get_lock(pte_t *ptep) { - unsigned long new = 0; + unsigned long value = 0; #ifdef CONFIG_PGSTE - unsigned long old; - - asm( - " lg %0,%2\n" - "0: lgr %1,%0\n" - " nihh %0,0xff7f\n" /* clear PCL bit in old */ - " oihh %1,0x0080\n" /* set PCL bit in new */ - " csg %0,%1,%2\n" - " jl 0b\n" - : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) - : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); + unsigned long *ptr = (unsigned long *)(ptep + PTRS_PER_PTE); + + do { + value = __atomic64_or_barrier(PGSTE_PCL_BIT, ptr); + } while (value & PGSTE_PCL_BIT); + value |= PGSTE_PCL_BIT; #endif - return __pgste(new); + return __pgste(value); } static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) { #ifdef CONFIG_PGSTE - asm( - " nihh %1,0xff7f\n" /* clear PCL bit */ - " stg %1,%0\n" - : "=Q" (ptep[PTRS_PER_PTE]) - : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) - : "cc", "memory"); + barrier(); + WRITE_ONCE(*(unsigned long *)(ptep + PTRS_PER_PTE), pgste_val(pgste) & ~PGSTE_PCL_BIT); #endif }