[v2,2/5] arm64: dts: qcom: sm8650: add LPASS LPI pin controller
Commit Message
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin
controller device node as part of audio subsystem in Qualcomm SM8650
SoC.
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
@@ -21,6 +21,7 @@
#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -2610,6 +2611,19 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ lpass_tlmm: pinctrl@6e80000 {
+ compatible = "qcom,sm8650-lpass-lpi-pinctrl";
+ reg = <0 0x06e80000 0 0x20000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+ };
+
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,sm8650-lpass-lpiaon-noc";
reg = <0 0x07400000 0 0x19080>;