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Thu, 30 Nov 2023 18:57:49 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 15/15] x86/resctrl: Update ABMC assignment on event configuration changes Date: Thu, 30 Nov 2023 18:57:20 -0600 Message-ID: <20231201005720.235639-16-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|DS7PR12MB6095:EE_ X-MS-Office365-Filtering-Correlation-Id: b1a08a67-e0a4-4c02-d2f8-08dbf2088b9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SpjN8XXetD0smoW/X5soFA+yOo9YqQFZI+jFjQsmQi/qN3X6Cz+WJ9RJRo4cItzeShwLqDUZG6j1T341wjv8mwZ5GjZgjhPssMX9Vq3wkObFyr26083E+sWrVMjwPVKtA95Ao5fJLKPFJB/C9eYGzV2N6R0UjzMhH52ChyXmh/5SgNF/mlQryj+SkxiQ7cktYETP1kxz3HiiwRq5BkE+1xWMqir3KS9ku0648P7fzHTV8fFYKd9bsGyNy5GuSQJk4WplKaGIAU0ah+sia30OxVWNBTfAo43Njjgx/5DZ5ebVgrx0Y5lioO2Mx+z+/gKKXNMZHtduQlxEysMB0v96ev5fcvj2Y9b0CR2dEY0yL+EwQiUutrR65aU3fg761U6oBXgaSnD3+W3wSj10YKzKVQBR6Af6hjBl4q98UYOwbIJP1wbfulk+gWoIMMKFoqZX3N8mYMA4XmmQ5HQiUG4SkTokSeWqe8vsbr80FABSiq9VRVeZ1u2AohTdw5HHl4EC/chpiA+UENotKS2Q68CWWAfM4EM+KxKe8YrhaRFOxn9ZZzOKzTmBJ/nFHZ39gjLq8H8NJ9QSHLltut7dz8CIcNkqjh0gUDcYAySeORrDRuQzppiZKccQs5E2+ihEbPLQDJjEY2wFTq0gsSe7b23jVnbX4FriFj/OS/So43pFselCow2iTrPxpncFI9G8H0NFgQZI/RofNsNX2HDHBly7+axVivEN6t5NX5gyiUgYfWFhvux8JsUU7rWSvZnyC7TMZJ1B1UpZmdDtJzUdG80cAA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(1800799012)(186009)(64100799003)(451199024)(82310400011)(46966006)(40470700004)(36840700001)(86362001)(40460700003)(83380400001)(26005)(1076003)(6666004)(7696005)(2616005)(47076005)(426003)(36860700001)(478600001)(44832011)(7416002)(8936002)(5660300002)(8676002)(41300700001)(336012)(2906002)(110136005)(966005)(16526019)(4326008)(316002)(15650500001)(81166007)(70206006)(70586007)(54906003)(36756003)(356005)(82740400003)(40480700001)(36900700001);DIR:OUT;SFP:1101; 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Thu, 30 Nov 2023 16:58:54 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039169384841365 X-GMAIL-MSGID: 1784039169384841365 When ABMC (Assignable Bandwidth Monitoring Counters) feature is enabled, bandwidth events can be read in following methods. 1. The contents of a specific counter can be read by setting the following fields in QM_EVTSEL: [ExtendedEvtID]=1, [EvtID]=L3CacheABMC and setting [RMID] to the desired counter ID. Reading QM_CTR will then return the contents of the specified counter. The E bit will be set if the counter configuration was invalid, or if an invalid counter ID was set in the QM_EVTSEL[RMID] field. Supporting this method requires changes in rmid_read interface. 2. Alternatively, the contents of a counter may be read by specifying an RMID and setting the [EvtID] to L3BWMonEvtn where n= {0,1}. If an assignable bandwidth counter is monitoring that RMID with a BwType bitmask that matches a QOS_EVT_CFG_n, that counter’s value will be returned when reading QM_CTR. However, if multiple counters have the same configuration, QM_CTR will return the value of the counter with the lowest CtrID. Method 2 is supported in here. For the ABMC counter assignment to work, the assignment needs to be updated to match BwType to the contents of the MSR QOS_EVT_CFG_n. So, update the ABMC assignment when event configuration changes. The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 6eca47673344..11890b4afb9f 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1768,6 +1768,38 @@ static ssize_t rdtgroup_monitor_state_write(struct kernfs_open_file *of, return ret ?: nbytes; } +static void rdtgroup_update_abmc(struct rdt_resource *r, + struct rdt_domain *d, u32 evtid) +{ + struct rdtgroup *prgrp, *crgrp; + int index, mon_state; + + if (evtid == QOS_L3_MBM_TOTAL_EVENT_ID) + mon_state = TOTAL_ASSIGN; + else + mon_state = LOCAL_ASSIGN; + + index = mon_event_config_index_get(evtid); + if (index == INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return; + } + + /* + * Update the assignment for all the monitor groups if the group + * is configured with ABMC assignment. + */ + list_for_each_entry(prgrp, &rdt_all_groups, rdtgroup_list) { + if (prgrp->mon.monitor_state & mon_state) + rdtgroup_abmc_domain(d, prgrp, evtid, index, 1); + + list_for_each_entry(crgrp, &prgrp->mon.crdtgrp_list, mon.crdtgrp_list) { + if (crgrp->mon.monitor_state & mon_state) + rdtgroup_abmc_domain(d, crgrp, evtid, index, 1); + } + } +} + static void mon_event_config_read(void *info) { struct mon_config_info *mon_info = info; @@ -1852,6 +1884,7 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); struct mon_config_info mon_info = {0}; int ret = 0; @@ -1892,6 +1925,13 @@ static int mbm_config_write_domain(struct rdt_resource *r, else goto out; + /* + * Event configuration changed for the domain, so Update + * the ABMC assignment. + */ + if (hw_res->abmc_enabled) + rdtgroup_update_abmc(r, d, evtid); + /* * When an Event Configuration is changed, the bandwidth counters * for all RMIDs and Events will be cleared by the hardware. The