diff mbox series

drm/msm/dpu: Correct UBWC settings for sc8280xp

Message ID 20231130192119.32538-1-robdclark@gmail.com
State New
Headers
Series drm/msm/dpu: Correct UBWC settings for sc8280xp |

Commit Message

Rob Clark Nov. 30, 2023, 7:21 p.m. UTC 
  From: Rob Clark <robdclark@chromium.org>

The UBWC settings need to match between the display and GPU.  When we
updated the GPU settings, we forgot to make the corresponding update on
the display side.

Reported-by: Steev Klimaszewski <steev@kali.org>
Fixes: 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 drivers/gpu/drm/msm/msm_mdss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Steev Klimaszewski Nov. 30, 2023, 9:24 p.m. UTC | #1 
On Thu, Nov 30, 2023 at 1:21 PM Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> The UBWC settings need to match between the display and GPU.  When we
> updated the GPU settings, we forgot to make the corresponding update on
> the display side.
>
> Reported-by: Steev Klimaszewski <steev@kali.org>
> Fixes: 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
>  drivers/gpu/drm/msm/msm_mdss.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 6865db1e3ce8..29bb38f0bb2c 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -545,7 +545,7 @@ static const struct msm_mdss_data sc8280xp_data = {
>         .ubwc_dec_version = UBWC_4_0,
>         .ubwc_swizzle = 6,
>         .ubwc_static = 1,
> -       .highest_bank_bit = 2,
> +       .highest_bank_bit = 3,
>         .macrotile_mode = 1,
>  };
>
> --
> 2.42.0
>
Tested on Lenovo Thinkpad X13s
Tested-by: Steev Klimaszewski <steev@kali.org>
Abhinav Kumar Nov. 30, 2023, 9:25 p.m. UTC | #2 
On 11/30/2023 11:21 AM, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> The UBWC settings need to match between the display and GPU.  When we
> updated the GPU settings, we forgot to make the corresponding update on
> the display side.
> 
> Reported-by: Steev Klimaszewski <steev@kali.org>
> Fixes: 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Dmitry Baryshkov Dec. 3, 2023, 11:26 a.m. UTC | #3 
On Thu, 30 Nov 2023 11:21:18 -0800, Rob Clark wrote:
> The UBWC settings need to match between the display and GPU.  When we
> updated the GPU settings, we forgot to make the corresponding update on
> the display side.
> 
> 

Applied, thanks!

[1/1] drm/msm/dpu: Correct UBWC settings for sc8280xp
      https://gitlab.freedesktop.org/lumag/msm/-/commit/0b414c731432

Best regards,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 6865db1e3ce8..29bb38f0bb2c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -545,7 +545,7 @@  static const struct msm_mdss_data sc8280xp_data = {
 	.ubwc_dec_version = UBWC_4_0,
 	.ubwc_swizzle = 6,
 	.ubwc_static = 1,
-	.highest_bank_bit = 2,
+	.highest_bank_bit = 3,
 	.macrotile_mode = 1,
 };