From patchwork Wed Nov 29 22:21:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 171633 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:296:b0:164:83eb:24d7 with SMTP id ek22csp16101rwb; Wed, 29 Nov 2023 14:22:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IG3eSJW8J+3uKDRpN60ydzm9HqDrvcaV2jpzEgTB9lDp0nbY5GiSTM3syBG7X38B0Lc/hMe X-Received: by 2002:a05:6a20:3941:b0:18b:937b:8312 with SMTP id r1-20020a056a20394100b0018b937b8312mr21150450pzg.16.1701296563496; Wed, 29 Nov 2023 14:22:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701296563; cv=none; d=google.com; s=arc-20160816; b=uk1u+0E6OgYk4jPv0a8YH5HSZhWDjEDT+13VLxlf0qAGMJFRz43lO+0wVoioS1fQ12 HvBsuRlUep47fdMMki86IpgCnwYHPYV2nOlf20MQiKpE8/kyIM6cXPBuJ7WiGzWvP5iJ 0sg370f4Sshr4ivhV+odou4zuQScNw2LMDDgE+tbNVUIPpzz9iyKU6lJNJ4kQ1xOV6wL 01IRZyzpS4PoUAaCv04+Edx5Z2VKA67i2BhT8eR/X6tQ5wWjuYfNAalFWn87XeRGaNgI KFeA5/pANAaBFljUsiBweWDLOPWFXJQNep2VzA7XuS4v+dZdcZf5kMGh1H4aPMmifm9r eLJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sGgNe47hfOL0E1vCn7aBp51fEVeNjfN/vjYbFErgLCY=; fh=d9G4dsZtlI8UONIvGKwhW94hCYEPGxy6CqYeKEG646A=; b=dh93PMsyf7GtBX9N22ADcMaSbSvdAMSoHVxBG/S8JCyARHrcf7kGy/HDQXBPZbc7Eo thDLaQa7KdZtSGx0YvwccTHaBFPjy3g5SGYDHywf7gvai/vRfLP2i+9PML4hrOMgDDR4 xmKLi8qnjRWKw5JQnZLBVTNaij4dzEIBgzW8W3hcNbHCFaDksiObE6jGIUx1nAXID5Io 4NaiN+wk6eerBgZlJr+eEZeutZ7OOuKPhi5LQdcmd9PUagdW5QzusMCnm51FQLlA3agI B/hCVJhvUFrOsTAPrNPJHaHFIy9UJSKLS+ciZ83F+nb6p+Npd7QUBjp/GZExKv27xV73 yU+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Wq3Wxo6q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id n2-20020a632702000000b005b90af19430si15053506pgn.595.2023.11.29.14.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 14:22:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Wq3Wxo6q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 819BD802C7E6; Wed, 29 Nov 2023 14:22:25 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343636AbjK2WWI (ORCPT + 99 others); Wed, 29 Nov 2023 17:22:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343526AbjK2WVl (ORCPT ); Wed, 29 Nov 2023 17:21:41 -0500 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8398A197; Wed, 29 Nov 2023 14:21:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296503; x=1732832503; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3uctqsFvdPRcO1F5mxpmLxaCC0IWGt+HEDKUw/EKGHQ=; b=Wq3Wxo6qfwv0PARXauAbAanewRzIglax0bJRmuCO9v2r5OqTcSQWcr6N ntQNeWTYKt3tNJS2i19OmmEJ0HZ1wjdgRkHOh9cEq0lJrwhsfsIGymTdd 4HtCGT2mHdw2YC16GOfzuWzGyYSN5ZFrzDtO8beE57xZ0GPgFjCq6Y6sU Y/74NTS3oCZ0AhaAVdjg1n3w/d/o9Qh8VPssKvTBAb4hDrLxceyAJoIRP ww57wN1w7TJ4cE6ZwAp5BWGZIMKXBoUjbeWM4VxUU1dRCKd+sHg+918aa MhxeST9zNse90QE8m6cj0iu+XB/P5S+hVBVGjDjgSmkgo5JiM+pRnMsX5 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937014" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937014" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070446" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070446" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 1136F580C4B; Wed, 29 Nov 2023 14:21:35 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 19/20] platform/x86/intel/pmc: Add debug attribute for Die C6 counter Date: Wed, 29 Nov 2023 14:21:31 -0800 Message-Id: <20231129222132.2331261-20-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 29 Nov 2023 14:22:25 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783938745172181459 X-GMAIL-MSGID: 1783938745172181459 Add a "die_c6_us_show" debugfs attribute. Reads the counter value using Intel Platform Monitoring Technology (PMT) driver API. This counter is useful for determining the idle residency of CPUs in the compute tile. Also adds a missing forward declaration for punit_ep which was declared in an earlier upstream commit but only used for the first time in this one. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - Change comment for crystal error and return value V4 - no change V3 - Split previous PATCH V2 13. Separates implementation (this patch) from platform specific use (next patch) V2 - Remove use of __func__ - Use HZ_PER_MHZ - Fix missing newlines in printks drivers/platform/x86/intel/pmc/core.c | 55 +++++++++++++++++++++++++++ drivers/platform/x86/intel/pmc/core.h | 4 ++ 2 files changed, 59 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 9d3a1b6ef622..983e3a8f4910 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,7 @@ #include #include "core.h" +#include "../pmt/telemetry.h" /* Maximum number of modes supported by platfoms that has low power mode capability */ const char *pmc_lpm_modes[] = { @@ -822,6 +824,47 @@ static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs); +static unsigned int pmc_core_get_crystal_freq(void) +{ + unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; + + if (boot_cpu_data.cpuid_level < 0x15) + return 0; + + eax_denominator = ebx_numerator = ecx_hz = edx = 0; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); + + if (ebx_numerator == 0 || eax_denominator == 0) + return 0; + + return ecx_hz; +} + +static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + u64 die_c6_res, count; + int ret; + + if (!pmcdev->crystal_freq) { + dev_warn_once(&pmcdev->pdev->dev, "Crystal frequency unavailable\n"); + return -ENXIO; + } + + ret = pmt_telem_read(pmcdev->punit_ep, pmcdev->die_c6_offset, + &count, 1); + if (ret) + return ret; + + die_c6_res = div64_u64(count * HZ_PER_MHZ, pmcdev->crystal_freq); + seq_printf(s, "%llu\n", die_c6_res); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us); + static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -1118,6 +1161,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_req_regs_fops); } + + if (pmcdev->has_die_c6) { + debugfs_create_file("die_c6_us_show", 0444, + pmcdev->dbgfs_dir, pmcdev, + &pmc_core_die_c6_us_fops); + } } static const struct x86_cpu_id intel_pmc_core_ids[] = { @@ -1212,6 +1261,10 @@ static void pmc_core_clean_structure(struct platform_device *pdev) pci_dev_put(pmcdev->ssram_pcidev); pci_disable_device(pmcdev->ssram_pcidev); } + + if (pmcdev->punit_ep) + pmt_telem_unregister_endpoint(pmcdev->punit_ep); + platform_set_drvdata(pdev, NULL); mutex_destroy(&pmcdev->lock); } @@ -1232,6 +1285,8 @@ static int pmc_core_probe(struct platform_device *pdev) if (!pmcdev) return -ENOMEM; + pmcdev->crystal_freq = pmc_core_get_crystal_freq(); + platform_set_drvdata(pdev, pmcdev); pmcdev->pdev = pdev; diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index 85b6f6ae4995..6d7673145f90 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -16,6 +16,8 @@ #include #include +struct telem_endpoint; + #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) #define PMC_BASE_ADDR_DEFAULT 0xFE000000 @@ -357,6 +359,7 @@ struct pmc { * @devs: pointer to an array of pmc pointers * @pdev: pointer to platform_device struct * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM + * @crystal_freq: crystal frequency from cpuid * @dbgfs_dir: path to debugfs interface * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers * used to read MPHY PG and PLL status are available @@ -374,6 +377,7 @@ struct pmc_dev { struct dentry *dbgfs_dir; struct platform_device *pdev; struct pci_dev *ssram_pcidev; + unsigned int crystal_freq; int pmc_xram_read_bit; struct mutex lock; /* generic mutex lock for PMC Core */