diff mbox series

[10/15] RISC-V: KVM: Allow Zihintntl extension for Guest/VM

Message ID	20231128145357.413321-11-apatel@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; From: Anup Patel <apatel@ventanamicro.com> To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org> Cc: Anup Patel <anup@brainfault.org>, Andrew Jones <ajones@ventanamicro.com>, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH 10/15] RISC-V: KVM: Allow Zihintntl extension for Guest/VM Date: Tue, 28 Nov 2023 20:23:52 +0530 Message-Id: <20231128145357.413321-11-apatel@ventanamicro.com> In-Reply-To: <20231128145357.413321-1-apatel@ventanamicro.com> References: <20231128145357.413321-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	KVM RISC-V report more ISA extensions through ONE_REG \| [00/15] KVM RISC-V report more ISA extensions through ONE_REG [01/15] KVM: riscv: selftests: Generate ISA extension reg_list using macros [02/15] RISC-V: KVM: Allow Zbc extension for Guest/VM [03/15] KVM: riscv: selftests: Add Zbc extension to get-reg-list test [04/15] RISC-V: KVM: Allow scalar crypto extensions for Guest/VM [05/15] KVM: riscv: selftests: Add scaler crypto extensions to get-reg-list test [06/15] RISC-V: KVM: Allow vector crypto extensions for Guest/VM [07/15] KVM: riscv: selftests: Add vector crypto extensions to get-reg-list test [08/15] RISC-V: KVM: Allow Zfh[min] extensions for Guest/VM [09/15] KVM: riscv: selftests: Add Zfh[min] extensions to get-reg-list test [10/15] RISC-V: KVM: Allow Zihintntl extension for Guest/VM [11/15] KVM: riscv: selftests: Add Zihintntl extension to get-reg-list test [12/15] RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VM [13/15] KVM: riscv: selftests: Add Zvfh[min] extensions to get-reg-list test [14/15] RISC-V: KVM: Allow Zfa extension for Guest/VM [15/15] KVM: riscv: selftests: Add Zfa extension to get-reg-list test

Commit Message

Anup Patel Nov. 28, 2023, 2:53 p.m. UTC

  We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zihintntl extension for Guest/VM.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu_onereg.c      | 2 ++
 2 files changed, 3 insertions(+)

Comments

Andrew Jones Jan. 15, 2024, 3:56 p.m. UTC | #1

On Tue, Nov 28, 2023 at 08:23:52PM +0530, Anup Patel wrote:
> We extend the KVM ISA extension ONE_REG interface to allow KVM
> user space to detect and enable Zihintntl extension for Guest/VM.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  arch/riscv/include/uapi/asm/kvm.h | 1 +
>  arch/riscv/kvm/vcpu_onereg.c      | 2 ++
>  2 files changed, 3 insertions(+)
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

diff mbox series

Patch

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index fa1a8e01b803..0ed5b0f8a230 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -162,6 +162,7 @@  enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZVKT,
 	KVM_RISCV_ISA_EXT_ZFH,
 	KVM_RISCV_ISA_EXT_ZFHMIN,
+	KVM_RISCV_ISA_EXT_ZIHINTNTL,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index ba418ac47e81..ba0a44b6b757 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -55,6 +55,7 @@  static const unsigned long kvm_isa_ext_arr[] = {
 	KVM_ISA_EXT_ARR(ZICOND),
 	KVM_ISA_EXT_ARR(ZICSR),
 	KVM_ISA_EXT_ARR(ZIFENCEI),
+	KVM_ISA_EXT_ARR(ZIHINTNTL),
 	KVM_ISA_EXT_ARR(ZIHINTPAUSE),
 	KVM_ISA_EXT_ARR(ZIHPM),
 	KVM_ISA_EXT_ARR(ZKND),
@@ -126,6 +127,7 @@  static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
 	case KVM_RISCV_ISA_EXT_ZICOND:
 	case KVM_RISCV_ISA_EXT_ZICSR:
 	case KVM_RISCV_ISA_EXT_ZIFENCEI:
+	case KVM_RISCV_ISA_EXT_ZIHINTNTL:
 	case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
 	case KVM_RISCV_ISA_EXT_ZIHPM:
 	case KVM_RISCV_ISA_EXT_ZKND: