Message ID | 20231128125959.1810039-17-nikunj@amd.com |
---|---|
State | New |
Headers |
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Series |
Add Secure TSC support for SNP guests
|
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Commit Message
Nikunj A. Dadhania
Nov. 28, 2023, 12:59 p.m. UTC
Now that all the required plumbing is done for enabling SNP Secure TSC
feature, add Secure TSC to snp features present list.
Set the CPUID feature bit (X86_FEATURE_SNP_SECURE_TSC) when SNP guest is
started with Secure TSC.
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
---
arch/x86/boot/compressed/sev.c | 3 ++-
arch/x86/mm/mem_encrypt.c | 10 ++++++++--
arch/x86/mm/mem_encrypt_amd.c | 4 +++-
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 454acd7a2daf..2829908602e5 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -375,7 +375,8 @@ static void enforce_vmpl0(void) * by the guest kernel. As and when a new feature is implemented in the * guest kernel, a corresponding bit should be added to the mask. */ -#define SNP_FEATURES_PRESENT MSR_AMD64_SNP_DEBUG_SWAP +#define SNP_FEATURES_PRESENT (MSR_AMD64_SNP_DEBUG_SWAP | \ + MSR_AMD64_SNP_SECURE_TSC) u64 snp_get_unsupported_features(u64 status) { diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index d5bcd63211de..b0db76dc4a9d 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -70,8 +70,14 @@ static void print_mem_encrypt_feature_info(void) pr_cont(" SEV-ES"); /* Secure Nested Paging */ - if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) - pr_cont(" SEV-SNP"); + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) { + pr_cont(" SEV-SNP\n"); + pr_cont("SNP Features active: "); + + /* SNP Secure TSC */ + if (cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) + pr_cont(" SECURE-TSC"); + } pr_cont("\n"); } diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index 8614c3028adb..2d1ab688c866 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -488,8 +488,10 @@ void __init sme_early_init(void) if (sev_status & MSR_AMD64_SEV_ES_ENABLED) x86_cpuinit.parallel_bringup = false; - if (sev_status & MSR_AMD64_SNP_SECURE_TSC) + if (sev_status & MSR_AMD64_SNP_SECURE_TSC) { + setup_force_cpu_cap(X86_FEATURE_SNP_SECURE_TSC); setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + } } void __init mem_encrypt_free_decrypted_mem(void)