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Tue, 28 Nov 2023 07:01:34 -0600 From: Nikunj A Dadhania To: , , , CC: , , , , , , , , Subject: [PATCH v6 11/16] x86/sev: Change TSC MSR behavior for Secure TSC enabled guests Date: Tue, 28 Nov 2023 18:29:54 +0530 Message-ID: <20231128125959.1810039-12-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128125959.1810039-1-nikunj@amd.com> References: <20231128125959.1810039-1-nikunj@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|PH7PR12MB6695:EE_ X-MS-Office365-Filtering-Correlation-Id: 99410a82-0b75-4e04-d9c2-08dbf01233f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VPminX5M31Ozexp7rhI8/WM0m1GOFxnBRevHR6+oc8wWe2nrr+GXzh7W8byLAuTxxErhUwiSWNj0RRoHczPJ1i9MVX7dBRcp/eiq57ZC2gs8mJ7ECmbdoNwznpkT8C57vYUt7CjmQDXSulnaZVW6q+9ykyeRMc2giGDI8QLS1QlDxNXtxyL3VCOa29/BO0XyXkl5n4Y4krWxcpJ5sbLIAozGbYtFrv+gmMIN1VHF09G7Lx1HYGkB1EqEjz39VUo4dkDmUZchX2KRzrr21L/kMlqU/fa8cBh4iRPIZ10mj44GrF70FAf2WfcQwE++59g3qKBNLLH2zCQGoaL2V8dJ50dLNBznr27ptxECoIiSt2tA5at5UKH2uOdFcBo6YwuUPaYHGAIA2+rBFGKzdywKEqwFKHS6MKKIhjIwSXu4JuPCn2bcSSEy+UmWLPRH1uCp9aRd0i4eeoE2LExTJruAzNMxUAUkCzXOXNxWx8A761lBP8XGzQXkpF+Ix+lO+R6WS4zDRp7DrjYYniLfg+HMC/rdXbBH2eHL4VZ99uJONE4SZrfQbly4eKdm+81ushOnoinf71rDhl0Cp3VQ294felvulMBWkJ/sllmW+g2P+33hnJXuTSR1I/mKFI2Ha367MgYfd2KXjyNBTCveLgsAjITfarYi97kpE9sowGScR5lG3mVesBAvwwGwtBFkEg7lcUA9KD97OYp/vvanxO1sxu/csO832wLuYxQ4A2aKbg8tNlDOAlhjsSX2WbXN2p9sFhFQ4+eMl4Z8s6bJAnsXqA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(136003)(346002)(230922051799003)(64100799003)(451199024)(186009)(1800799012)(82310400011)(40470700004)(46966006)(36840700001)(6666004)(8936002)(4326008)(8676002)(7696005)(54906003)(110136005)(70586007)(70206006)(316002)(478600001)(40460700003)(81166007)(356005)(47076005)(36756003)(41300700001)(1076003)(26005)(2906002)(16526019)(36860700001)(2616005)(40480700001)(83380400001)(336012)(426003)(7416002)(5660300002)(82740400003)(36900700001);DIR:OUT;SFP:1101; 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Tue, 28 Nov 2023 05:02:40 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783812920111936098 X-GMAIL-MSGID: 1783812920111936098 Secure TSC enabled guests should not write MSR_IA32_TSC(10H) register as the subsequent TSC value reads are undefined. MSR_IA32_TSC related accesses should not exit to the hypervisor for such guests. Accesses to MSR_IA32_TSC needs special handling in the #VC handler for the guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored, and reads of MSR_IA32_TSC should return the result of the RDTSC instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky --- arch/x86/kernel/sev.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 1cb6c66d1601..602988080312 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1266,6 +1266,30 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) /* Is it a WRMSR? */ exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; + /* + * TSC related accesses should not exit to the hypervisor when a + * guest is executing with SecureTSC enabled, so special handling + * is required for accesses of MSR_IA32_TSC: + * + * Writes: Writing to MSR_IA32_TSC can cause subsequent reads + * of the TSC to return undefined values, so ignore all + * writes. + * Reads: Reads of MSR_IA32_TSC should return the current TSC + * value, use the value returned by RDTSC. + */ + if (regs->cx == MSR_IA32_TSC && cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) { + u64 tsc; + + if (exit_info_1) + return ES_OK; + + tsc = rdtsc(); + regs->ax = UINT_MAX & tsc; + regs->dx = UINT_MAX & (tsc >> 32); + + return ES_OK; + } + ghcb_set_rcx(ghcb, regs->cx); if (exit_info_1) { ghcb_set_rax(ghcb, regs->ax);