Message ID | 20231128045415.210682-3-aford173@gmail.com |
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Mon, 27 Nov 2023 20:54:31 -0800 (PST) From: Adam Ford <aford173@gmail.com> To: linux-arm-kernel@lists.infradead.org Cc: aford@beaconembeded.com, Adam Ford <aford173@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: imx8mm: Slow default video_pll1 clock rate Date: Mon, 27 Nov 2023 22:54:15 -0600 Message-Id: <20231128045415.210682-3-aford173@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231128045415.210682-1-aford173@gmail.com> References: <20231128045415.210682-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); 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Series |
[1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks
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Commit Message
Adam Ford
Nov. 28, 2023, 4:54 a.m. UTC
Since commit 8208181fe536 ("clk: imx: composite-8m:
Add imx8m_divider_determine_rate") the lcdif controller has
had the ability to set the lcdif_pixel rate which propagates
up the tree and sets the video_pll1 rate automatically.
By setting this value low, it will force the recalculation of
video_pll1 to the lowest rate needed by lcdif instead of
dividing a larger clock down to the desired clock speed. This
has the advantage of being able to lower the video_pll1 rate
from 594MHz to 148.5MHz when operating at 1080p. It can go even
lower when operating at lower resolutions and refresh rates.
Signed-off-by: Adam Ford <aford173@gmail.com>
Comments
On 28.11.23 05:54, Adam Ford wrote: > Since commit 8208181fe536 ("clk: imx: composite-8m: > Add imx8m_divider_determine_rate") the lcdif controller has > had the ability to set the lcdif_pixel rate which propagates > up the tree and sets the video_pll1 rate automatically. > > By setting this value low, it will force the recalculation of > video_pll1 to the lowest rate needed by lcdif instead of > dividing a larger clock down to the desired clock speed. This > has the advantage of being able to lower the video_pll1 rate > from 594MHz to 148.5MHz when operating at 1080p. It can go even > lower when operating at lower resolutions and refresh rates. > > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index a3dae114c20e..669fdd2c54e4 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 { > assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, > <&clk IMX8MM_SYS_PLL2_1000M>, > <&clk IMX8MM_SYS_PLL1_800M>; > - assigned-clock-rates = <594000000>, <500000000>, <200000000>; > + assigned-clock-rates = <24000000>, <500000000>, <200000000>; > interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; > status = "disabled"; Thanks for the cleanup! Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a3dae114c20e..669fdd2c54e4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 { assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, <&clk IMX8MM_SYS_PLL2_1000M>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <594000000>, <500000000>, <200000000>; + assigned-clock-rates = <24000000>, <500000000>, <200000000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; status = "disabled";