diff mbox series

[2/3] arm64: dts: imx8mm: Remove video_pll1 clock rate from clk node

Message ID 20231128045415.210682-2-aford173@gmail.com
State New
Headers
Series [1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks |

Commit Message

Adam Ford Nov. 28, 2023, 4:54 a.m. UTC 
  There are two clock-rate assignments for video_pll1, and the
only one it should really have belongs inside the lcdif node,
since it's the only consumer of this clock.  Remove it from
the clk node.

Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Frieder Schrempf Nov. 30, 2023, 3:46 p.m. UTC | #1 
On 28.11.23 05:54, Adam Ford wrote:
> There are two clock-rate assignments for video_pll1, and the
> only one it should really have belongs inside the lcdif node,
> since it's the only consumer of this clock.  Remove it from
> the clk node.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 8d872568231d..a3dae114c20e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -647,7 +647,6 @@ clk: clock-controller@30380000 {
>  						<&clk IMX8MM_CLK_AUDIO_AHB>,
>  						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
>  						<&clk IMX8MM_SYS_PLL3>,
> -						<&clk IMX8MM_VIDEO_PLL1>,
>  						<&clk IMX8MM_AUDIO_PLL1>;
>  				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
>  							 <&clk IMX8MM_ARM_PLL_OUT>,
> @@ -657,7 +656,6 @@ clk: clock-controller@30380000 {
>  							<400000000>,
>  							<400000000>,
>  							<750000000>,
> -							<594000000>,
>  							<393216000>;
>  			};
>  

Thanks for the cleanup!

Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL
i.MX8MM
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 8d872568231d..a3dae114c20e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -647,7 +647,6 @@  clk: clock-controller@30380000 {
 						<&clk IMX8MM_CLK_AUDIO_AHB>,
 						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MM_SYS_PLL3>,
-						<&clk IMX8MM_VIDEO_PLL1>,
 						<&clk IMX8MM_AUDIO_PLL1>;
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
 							 <&clk IMX8MM_ARM_PLL_OUT>,
@@ -657,7 +656,6 @@  clk: clock-controller@30380000 {
 							<400000000>,
 							<400000000>,
 							<750000000>,
-							<594000000>,
 							<393216000>;
 			};