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Mon, 27 Nov 2023 20:54:28 -0800 (PST) From: Adam Ford <aford173@gmail.com> To: linux-arm-kernel@lists.infradead.org Cc: aford@beaconembeded.com, Adam Ford <aford173@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks Date: Mon, 27 Nov 2023 22:54:13 -0600 Message-Id: <20231128045415.210682-1-aford173@gmail.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); 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Series |
[1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks
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Commit Message
Adam Ford
Nov. 28, 2023, 4:54 a.m. UTC
The device tree clock structure for the mipi_dsi is
unnecessarily redundant.
The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
already IMX8MM_CLK_24M, so there is no need to set the
parent-child relationship between them. The default clock
rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
already defined to be 266MHz and 24MHz respectively,
so there is no need to define those clock rates.
On i.MX8M[MNP] the samsung,pll-clock-frequency is not
necessary, because the driver will read it from sclk_mipi
which is also already set to 24MHz making it also
redundant.
Signed-off-by: Adam Ford <aford173@gmail.com>
Comments
On 28.11.23 05:54, Adam Ford wrote: > The device tree clock structure for the mipi_dsi is > unnecessarily redundant. > > The default clock parent of IMX8MM_CLK_DSI_PHY_REF is > already IMX8MM_CLK_24M, so there is no need to set the > parent-child relationship between them. The default clock > rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are > already defined to be 266MHz and 24MHz respectively, > so there is no need to define those clock rates. > > On i.MX8M[MNP] the samsung,pll-clock-frequency is not > necessary, because the driver will read it from sclk_mipi > which is also already set to 24MHz making it also > redundant. > > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 738024baaa57..8d872568231d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -1151,12 +1151,8 @@ mipi_dsi: dsi@32e10000 { > clocks = <&clk IMX8MM_CLK_DSI_CORE>, > <&clk IMX8MM_CLK_DSI_PHY_REF>; > clock-names = "bus_clk", "sclk_mipi"; > - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, > - <&clk IMX8MM_CLK_DSI_PHY_REF>; > - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, > - <&clk IMX8MM_CLK_24M>; > - assigned-clock-rates = <266000000>, <24000000>; > - samsung,pll-clock-frequency = <24000000>; > + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; > interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; > status = "disabled"; Thanks for the cleanup! Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM
On Mon, Nov 27, 2023 at 10:54:13PM -0600, Adam Ford wrote: > The device tree clock structure for the mipi_dsi is > unnecessarily redundant. > > The default clock parent of IMX8MM_CLK_DSI_PHY_REF is > already IMX8MM_CLK_24M, so there is no need to set the > parent-child relationship between them. The default clock > rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are > already defined to be 266MHz and 24MHz respectively, > so there is no need to define those clock rates. > > On i.MX8M[MNP] the samsung,pll-clock-frequency is not > necessary, because the driver will read it from sclk_mipi > which is also already set to 24MHz making it also > redundant. > > Signed-off-by: Adam Ford <aford173@gmail.com> Applied all, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 738024baaa57..8d872568231d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1151,12 +1151,8 @@ mipi_dsi: dsi@32e10000 { clocks = <&clk IMX8MM_CLK_DSI_CORE>, <&clk IMX8MM_CLK_DSI_PHY_REF>; clock-names = "bus_clk", "sclk_mipi"; - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, - <&clk IMX8MM_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_CLK_24M>; - assigned-clock-rates = <266000000>, <24000000>; - samsung,pll-clock-frequency = <24000000>; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; status = "disabled";