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Mon, 27 Nov 2023 14:05:17 -0800 (PST) From: Charlie Jenkins Date: Mon, 27 Nov 2023 14:05:00 -0800 Subject: [PATCH v4 2/2] riscv: Correct type casting in module loading MIME-Version: 1.0 Message-Id: <20231127-module_linking_freeing-v4-2-a2ca1d7027d0@rivosinc.com> References: <20231127-module_linking_freeing-v4-0-a2ca1d7027d0@rivosinc.com> In-Reply-To: <20231127-module_linking_freeing-v4-0-a2ca1d7027d0@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Ron Economos , Samuel Holland , Andreas Schwab Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701122714; l=1122; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=gKtfd5M4f/12qT968kmTbpH+FPE5A73SSgTlwm9+2vg=; b=n0mTJP+LYH0N4DSIuQTOKLB4SExsBvS4/o0PIOTxDPx23GVbSNKIkufpsBdKBOvb6R7paXCcV fHMdu6GDl3eAEQWplkrU6P3PL2M0orVhoFEVV10vqJHYN2WN6KTtQAy X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 27 Nov 2023 14:05:41 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783756509312329756 X-GMAIL-MSGID: 1783756509312329756 Use __le16 with le16_to_cpu. Fixes: 8fd6c5142395 ("riscv: Add remaining module relocations") Signed-off-by: Charlie Jenkins Reviewed-by: Samuel Holland Tested-by: Samuel Holland Tested-by: Lad Prabhakar #On --- arch/riscv/kernel/module.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 53593fe58cd8..aac019ed63b1 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -55,7 +55,7 @@ static bool riscv_insn_valid_32bit_offset(ptrdiff_t val) static int riscv_insn_rmw(void *location, u32 keep, u32 set) { - u16 *parcel = location; + __le16 *parcel = location; u32 insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16; insn &= keep; @@ -68,7 +68,7 @@ static int riscv_insn_rmw(void *location, u32 keep, u32 set) static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set) { - u16 *parcel = location; + __le16 *parcel = location; u16 insn = le16_to_cpu(*parcel); insn &= keep;