Message ID | 20231126232746.264302-2-emil.renner.berthing@canonical.com |
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State | New |
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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y10-20020a170902b48a00b001cfb52ebffesm3123853plr.147.2023.11.26.15.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 15:28:04 -0800 (PST) From: Emil Renner Berthing <emil.renner.berthing@canonical.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Emil Renner Berthing <kernel@esmil.dk>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Subject: [PATCH v1 1/8] riscv: errata: Add StarFive JH7100 errata Date: Mon, 27 Nov 2023 00:27:39 +0100 Message-Id: <20231126232746.264302-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126232746.264302-1-emil.renner.berthing@canonical.com> References: <20231126232746.264302-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=0.6 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Sun, 26 Nov 2023 15:28:23 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783671088650594423 X-GMAIL-MSGID: 1783671088650594423 |
Series |
Add JH7100 errata and update device tree
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Commit Message
Emil Renner Berthing
Nov. 26, 2023, 11:27 p.m. UTC
This not really an errata, but since the JH7100 was made before
the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
arch/riscv/Kconfig.errata | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
Comments
On Mon, Nov 27, 2023 at 12:27:39AM +0100, Emil Renner Berthing wrote: > This not really an errata, but since the JH7100 was made before > the standard Zicbom extension it needs the DMA_GLOBAL_POOL and > RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/Kconfig.errata | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata > index e2c731cfed8c..692de149141f 100644 > --- a/arch/riscv/Kconfig.errata > +++ b/arch/riscv/Kconfig.errata > @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 > > If you don't know what to do here, say "Y". > > +config ERRATA_STARFIVE_JH7100 > + bool "StarFive JH7100 support" > + depends on ARCH_STARFIVE && NONPORTABLE > + select DMA_GLOBAL_POOL > + select RISCV_DMA_NONCOHERENT > + select RISCV_NONSTANDARD_CACHE_OPS > + select SIFIVE_CCACHE > + default n > + help > + The StarFive JH7100 was a test chip for the JH7110 and has > + caches that are non-coherent with respect to peripheral DMAs. > + It was designed before the Zicbom extension so needs non-standard > + cache operations through the SiFive cache controller. > + > + Say "Y" if you want to support the BeagleV Starlight and/or > + StarFive VisionFive V1 boards. > + > config ERRATA_THEAD > bool "T-HEAD errata" > depends on RISCV_ALTERNATIVE > -- > 2.40.1 >
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..692de149141f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE_JH7100 + bool "StarFive JH7100 support" + depends on ARCH_STARFIVE && NONPORTABLE + select DMA_GLOBAL_POOL + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + select SIFIVE_CCACHE + default n + help + The StarFive JH7100 was a test chip for the JH7110 and has + caches that are non-coherent with respect to peripheral DMAs. + It was designed before the Zicbom extension so needs non-standard + cache operations through the SiFive cache controller. + + Say "Y" if you want to support the BeagleV Starlight and/or + StarFive VisionFive V1 boards. + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE