diff mbox series

bus: ti-sysc: Flush posted write only after srst_udelay

Message ID 20231124104133.19100-1-tony@atomide.com
State New
Headers
Series bus: ti-sysc: Flush posted write only after srst_udelay |

Commit Message

Tony Lindgren Nov. 24, 2023, 10:41 a.m. UTC 
  Commit 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before
reset") caused a regression reproducable on omap4 duovero where the ISS
target module can produce interconnect errors on boot. Turns out the
registers are not accessible until after a delay for devices needing
a ti,sysc-delay-us value.

Let's fix this by flushing the posted write only after the reset delay.
We do flushing also for ti,sysc-delay-us using devices as that should
trigger an interconnect error if the delay is not properly configured.

Let's also add some comments while at it.

Fixes: 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before reset")
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 drivers/bus/ti-sysc.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

Comments

Greg KH Nov. 24, 2023, 11:48 a.m. UTC | #1 
On Fri, Nov 24, 2023 at 12:41:33PM +0200, Tony Lindgren wrote:
> Commit 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before
> reset") caused a regression reproducable on omap4 duovero where the ISS
> target module can produce interconnect errors on boot. Turns out the
> registers are not accessible until after a delay for devices needing
> a ti,sysc-delay-us value.
> 
> Let's fix this by flushing the posted write only after the reset delay.
> We do flushing also for ti,sysc-delay-us using devices as that should
> trigger an interconnect error if the delay is not properly configured.
> 
> Let's also add some comments while at it.
> 
> Fixes: 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before reset")
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  drivers/bus/ti-sysc.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)

Hi,

This is the friendly patch-bot of Greg Kroah-Hartman.  You have sent him
a patch that has triggered this response.  He used to manually respond
to these common problems, but in order to save his sanity (he kept
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You are receiving this message because of the following common error(s)
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If you wish to discuss this problem further, or you have questions about
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diff mbox series

Patch

diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -2158,13 +2158,23 @@  static int sysc_reset(struct sysc *ddata)
 		sysc_val = sysc_read_sysconfig(ddata);
 		sysc_val |= sysc_mask;
 		sysc_write(ddata, sysc_offset, sysc_val);
-		/* Flush posted write */
+
+		/*
+		 * Some devices need a delay before reading registers
+		 * after reset. Presumably a srst_udelay is not needed
+		 * for devices that use a rstctrl register reset.
+		 */
+		if (ddata->cfg.srst_udelay)
+			fsleep(ddata->cfg.srst_udelay);
+
+		/*
+		 * Flush posted write. For devices needing srst_udelay
+		 * this should trigger an interconnect error if the
+		 * srst_udelay value is needed but not configured.
+		 */
 		sysc_val = sysc_read_sysconfig(ddata);
 	}
 
-	if (ddata->cfg.srst_udelay)
-		fsleep(ddata->cfg.srst_udelay);
-
 	if (ddata->post_reset_quirk)
 		ddata->post_reset_quirk(ddata);