| Message ID | 20231123152639.561231-16-gregory.clement@bootlin.com |
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From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Paul Burton <paulburton@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,
Tawfik Bayouk <tawfik.bayouk@mobileye.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>, =?utf-8?q?Th=C3=A9o_Lebr?=
=?utf-8?q?un?= <theo.lebrun@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>, Arnd Bergmann <arnd@arndb.de>,
=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH v2 15/21] dt-bindings: mips: cpu: Add I-Class I6500
Multiprocessor Core
Date: Thu, 23 Nov 2023 16:26:32 +0100
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| Series |
Add support for the Mobileye EyeQ5 SoC
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Commit Message
Gregory CLEMENT
Nov. 23, 2023, 3:26 p.m. UTC
The MIPS Warrior I-class I6500 was announced by Imagination Technologies in 2016 and is used in the Mobileye SoC EyeQ5. Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- Documentation/devicetree/bindings/mips/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
Comments
On 23/11/2023 16:26, Gregory CLEMENT wrote: > The MIPS Warrior I-class I6500 was announced by Imagination > Technologies in 2016 and is used in the Mobileye SoC EyeQ5. > > Acked-by: Arnd Bergmann <arnd@arndb.de> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > Documentation/devicetree/bindings/mips/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml > index cf382dea3922c..b5165cf103e94 100644 > --- a/Documentation/devicetree/bindings/mips/cpus.yaml > +++ b/Documentation/devicetree/bindings/mips/cpus.yaml > @@ -39,6 +39,7 @@ properties: > - mti,mips24KEc > - mti,mips14KEc > - mti,mips14Kc > + - img,i6500 Don't break the order of entries. Best regards, Krzysztof
On Thu, Nov 23, 2023 at 04:26:32PM +0100, Gregory CLEMENT wrote: > The MIPS Warrior I-class I6500 was announced by Imagination > Technologies in 2016 and is used in the Mobileye SoC EyeQ5. > > Acked-by: Arnd Bergmann <arnd@arndb.de> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> One more time: Reviewed-by: Serge Semin <fancer.lancer@gmail.com> -Serge(y) > --- > Documentation/devicetree/bindings/mips/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml > index cf382dea3922c..b5165cf103e94 100644 > --- a/Documentation/devicetree/bindings/mips/cpus.yaml > +++ b/Documentation/devicetree/bindings/mips/cpus.yaml > @@ -39,6 +39,7 @@ properties: > - mti,mips24KEc > - mti,mips14KEc > - mti,mips14Kc > + - img,i6500 > > reg: > maxItems: 1 > -- > 2.42.0 > >
Hello Krzysztof, > On 23/11/2023 16:26, Gregory CLEMENT wrote: >> The MIPS Warrior I-class I6500 was announced by Imagination >> Technologies in 2016 and is used in the Mobileye SoC EyeQ5. >> >> Acked-by: Arnd Bergmann <arnd@arndb.de> >> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> >> --- >> Documentation/devicetree/bindings/mips/cpus.yaml | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml >> index cf382dea3922c..b5165cf103e94 100644 >> --- a/Documentation/devicetree/bindings/mips/cpus.yaml >> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml >> @@ -39,6 +39,7 @@ properties: >> - mti,mips24KEc >> - mti,mips14KEc >> - mti,mips14Kc >> + - img,i6500 > > Don't break the order of entries. Do you mean alphabetic order ? because actually the entries are not really in alphabetic order. Should I send first, a patch like the following one ? diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index cf382dea3922c..9bc47868d28b6 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,22 +23,22 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 - - ingenic,xburst-mxu1.0 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 + - ingenic,xburst-mxu1.0 - ingenic,xburst2-fpu2.1-mxu2.1-smt - loongson,gs264 - mips,m14Kc - - mips,mips4Kc - - mips,mips4KEc - - mips,mips24Kc + - mips,mips1004Kc - mips,mips24KEc + - mips,mips24Kc + - mips,mips4KEc + - mips,mips4Kc - mips,mips74Kc - - mips,mips1004Kc - mti,interaptiv - - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,mips24KEc reg: maxItems: 1 Regards, Gregory > > Best regards, > Krzysztof >
On 30/11/2023 11:51, Gregory CLEMENT wrote: > Hello Krzysztof, > >> On 23/11/2023 16:26, Gregory CLEMENT wrote: >>> The MIPS Warrior I-class I6500 was announced by Imagination >>> Technologies in 2016 and is used in the Mobileye SoC EyeQ5. >>> >>> Acked-by: Arnd Bergmann <arnd@arndb.de> >>> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> >>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> >>> --- >>> Documentation/devicetree/bindings/mips/cpus.yaml | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml >>> index cf382dea3922c..b5165cf103e94 100644 >>> --- a/Documentation/devicetree/bindings/mips/cpus.yaml >>> +++ b/Documentation/devicetree/bindings/mips/cpus.yaml >>> @@ -39,6 +39,7 @@ properties: >>> - mti,mips24KEc >>> - mti,mips14KEc >>> - mti,mips14Kc >>> + - img,i6500 >> >> Don't break the order of entries. > > Do you mean alphabetic order ? I guess they are not fully ordered, but adding items to the end of the list is for sure not improving the order. > > because actually the entries are not really in alphabetic order. > > Should I send first, a patch like the following one ? I wouldn't care about fixing existing order, so just the entry could be around the ones 'i' because that part is ordered. All entries are ordered by vendor prefix, so adding 'img' after 'mti' for sure breaks that order. > Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index cf382dea3922c..b5165cf103e94 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -39,6 +39,7 @@ properties: - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - img,i6500 reg: maxItems: 1