From patchwork Tue Nov 21 11:56:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167694 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565463vqb; Tue, 21 Nov 2023 04:00:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHFwuH/qIvAgBwjpTU1PpCGN7UdEuhfimMOw8E56OeNUH7ClbA8CYAhcrn4bwVr67vvlcdj X-Received: by 2002:a17:902:6a87:b0:1cc:4a23:c5fc with SMTP id n7-20020a1709026a8700b001cc4a23c5fcmr8003421plk.2.1700568004075; Tue, 21 Nov 2023 04:00:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568004; cv=none; d=google.com; s=arc-20160816; b=xgDwhZROHOgJNpmOXEVqNWj1qm4UXE3ska6TWklRMB2qPzMeqtUVkQoQ+AZA9od5cU ZR+BHkv86ZjTbjX8TdmaI/6oZPi/HffrbANUdLcu66a2WJIPOFSvX7jqxo2cc/zPSDIk pwLaNmpEaZ8wucOWlkOfXGRVOZloxstxC9ZcCBwvOcO8uOELOoocobY+ceBf8yq4VZB6 AZN4YXkP2F2A6NhM1u3kbD2OMxVETVP9cSy4wVKlY88JoumKiADnG5J0Ls3FI6vxRRyn kxK0dzlUQFX7xmmrW18fxPxHoaf3/t7JdJyLEv3rpL+vQ4Hg41+QvTqRqO/RYzLJWGXn iHAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2nSvjwhp8KEX+f10c8PjMOZ1/nuFqQp7c5iuH1zb1GM=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=ewR/mjvOLjTRcjI8QNoIB1GXRNJizQI3pRPNcacm+Q17xuxfbZbI4o6Q8yT4cWrdzl w63oAJgUZuABkN/EVS/Z7j0XuCfPXb0bRQPnCFZd11UUDIKtbpx5jAwnbWxQzcy5GHHA ZEkA1plz5xgjDpAKj0/kcMjN92fUlWk2CFChq/LOH3SY1OIujEuQPONGeL4n54Zpvweg PI8vSiBIEiAUKc4PXSexFMoxlwdXcETVaLWA5SDR3lN68Eeqs+0+4cQ/+fhCaKSDX2Uc zWBvuzNMV8F6psi9DWPYzQyKJv7Ad4D5ouVNCaasL+XeKbNz6i1lDGmuowBLGtoOs043 Tz1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=AzcJTJtc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id j11-20020a170902da8b00b001cf747e89c1si195430plx.145.2023.11.21.04.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=AzcJTJtc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D9F6A81121CA; Tue, 21 Nov 2023 03:58:12 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234661AbjKUL56 (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234646AbjKUL45 (ORCPT ); Tue, 21 Nov 2023 06:56:57 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B05D7BA; Tue, 21 Nov 2023 03:56:53 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A94466607286; Tue, 21 Nov 2023 11:56:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567812; bh=6uV/aa1GXqZk9w0ZoiU/aw6OTSIwDj0KZLX0pQNrucc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AzcJTJtcns2hZVQxPv//hCU1Ktg1kQPx1j+4phznifkdcfkG6kMM+QLmJDK1YlFxP RSq201iTG5sE8ggnON3rAC6anpXaj8FKY2VYWKYwQEr789kooV+0FamtKG9wfY41F9 NVni+Ire/E2C1Xaw60EzwIdhA4cABDHzsvUN2Dq85o+edij3aud1JL4lXXJTGAVVAS 3er6SsEHOFfC1hNpZkPix07W7GIDAZ0ulKN6wWP96LOARRWiJmLhY1eK7eqf/QIe76 miwiqWJceqJvECbus/En8QaCH5FKdYyMsjzEss9o4Bu6WbDdqkusT+D9YBFZ6k2e33 M1ScoW6Kkwdaw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 20/20] arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace Date: Tue, 21 Nov 2023 12:56:24 +0100 Message-ID: <20231121115624.56855-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:13 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174795139664863 X-GMAIL-MSGID: 1783174795139664863 Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Also, reduce the LVTS_AP iospace to 0xc00, because that's exactly where SVS starts. - LVTS_AP start: 0x1100b000 length: 0xc00 - SVS start: 0x1100bc00 length: 0x400 Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 54c674c45b49..54debd4cf8e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1115,7 +1115,7 @@ spi0: spi@1100a000 { lvts_ap: thermal-sensor@1100b000 { compatible = "mediatek,mt8195-lvts-ap"; - reg = <0 0x1100b000 0 0x1000>; + reg = <0 0x1100b000 0 0xc00>; interrupts = ; clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; @@ -1124,6 +1124,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8195-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names = "svs_rst"; + }; + disp_pwm0: pwm@1100e000 { compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1682,6 +1694,9 @@ lvts_efuse_data1: lvts1-calib@1bc { lvts_efuse_data2: lvts2-calib@1d0 { reg = <0x1d0 0x38>; }; + svs_calib_data: svs-calib@580 { + reg = <0x580 0x64>; + }; }; u3phy2: t-phy@11c40000 {