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([178.233.24.52]) by smtp.gmail.com with ESMTPSA id o1-20020adfeac1000000b0032dab20e773sm11077833wrn.69.2023.11.15.09.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 09:08:35 -0800 (PST) From: Alper Nebi Yasak To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , linux-mediatek@lists.infradead.org, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger , Chen-Yu Tsai , linux-clk@vger.kernel.org, AngeloGioacchino Del Regno , Alper Nebi Yasak Subject: [PATCH v2 2/2] arm64: dts: mediatek: mt8173: Fix timer 13 MHz clock description Date: Wed, 15 Nov 2023 20:06:25 +0300 Message-ID: <20231115170825.908640-2-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115170825.908640-1-alpernebiyasak@gmail.com> References: <20231115170825.908640-1-alpernebiyasak@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 15 Nov 2023 09:09:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782650661754838205 X-GMAIL-MSGID: 1782650661754838205 A previous patch fixes an issue with the mt8173-infracfg clock driver when working as a module, but has the side effect of skipping set up of CLK_INFRA_CLK_13M in that case. This clock is used by the timer device. Similar to the MT8183, MT8192, MT8195 and MT8186 cases [1], change the input clock of the timer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Also remove the RTC clock from the timer node while we're here. According to commit 59311b19d7f63 ("clocksource/drivers/timer-mediatek: Add system timer bindings") it is no longer used. [1] https://lore.kernel.org/all/20221201084229.3464449-1-wenst@chromium.org/ Signed-off-by: Alper Nebi Yasak --- Tested on a MT8173 Chromebook. But I'm not sure I understand all of this, so review with a pinch of salt. Do we need to remove CLK_INFRA_CLK_13M from mt8173-infracfg after this? Changes in v2: - Add this patch arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index c47d7d900f28..9062ca124d69 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -244,6 +244,15 @@ psci { cpu_on = <0x84000003>; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -530,8 +539,7 @@ timer: timer@10008000 { "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; interrupts = ; - clocks = <&infracfg CLK_INFRA_CLK_13M>, - <&topckgen CLK_TOP_RTC_SEL>; + clocks = <&clk13m>; }; pwrap: pwrap@1000d000 {