diff mbox series

[1/9] net: mdio: ipq4019: increase eth_ldo_rdy for ipq5332 platform

Message ID 20231115032515.4249-2-quic_luoj@quicinc.com
State New
Headers
Series add MDIO changes on ipq5332 platform |

Commit Message

Jie Luo Nov. 15, 2023, 3:25 a.m. UTC 
  There are two PCS(UNIPHY) supported in SOC side on ipq5332,
and three PCS(UNIPHY) supported on ipq9574.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/mdio/mdio-ipq4019.c | 55 +++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 23 deletions(-)

Comments

Andrew Lunn Nov. 15, 2023, 1:44 p.m. UTC | #1 
> +	for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) {
> +		if (priv->eth_ldo_rdy[ret]) {
> +			val = readl(priv->eth_ldo_rdy[ret]);
> +			val |= BIT(0);
> +			writel(val, priv->eth_ldo_rdy[ret]);
> +			fsleep(IPQ_PHY_SET_DELAY_US);
> +		}

Please add a new variable, rather than use ret this way.

> +	for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) {
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, ret + 1);
> +		if (res)
> +			priv->eth_ldo_rdy[ret] = devm_ioremap(&pdev->dev,

same here.

    Andrew

---
pw-bot: cr
Jie Luo Nov. 16, 2023, 9:35 a.m. UTC | #2 
On 11/15/2023 9:44 PM, Andrew Lunn wrote:
>> +	for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) {
>> +		if (priv->eth_ldo_rdy[ret]) {
>> +			val = readl(priv->eth_ldo_rdy[ret]);
>> +			val |= BIT(0);
>> +			writel(val, priv->eth_ldo_rdy[ret]);
>> +			fsleep(IPQ_PHY_SET_DELAY_US);
>> +		}
> 
> Please add a new variable, rather than use ret this way.

OK, will add it in the next patch set.

> 
>> +	for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) {
>> +		res = platform_get_resource(pdev, IORESOURCE_MEM, ret + 1);
>> +		if (res)
>> +			priv->eth_ldo_rdy[ret] = devm_ioremap(&pdev->dev,
> 
> same here.

Ok.

> 
>      Andrew
> 
> ---
> pw-bot: cr
Krzysztof Kozlowski Nov. 16, 2023, 11:57 a.m. UTC | #3 
On 15/11/2023 04:25, Luo Jie wrote:
> There are two PCS(UNIPHY) supported in SOC side on ipq5332,
> and three PCS(UNIPHY) supported on ipq9574.
> 
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  drivers/net/mdio/mdio-ipq4019.c | 55 +++++++++++++++++++--------------
>  1 file changed, 32 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
> index abd8b508ec16..9d444f5f7efb 100644
> --- a/drivers/net/mdio/mdio-ipq4019.c
> +++ b/drivers/net/mdio/mdio-ipq4019.c
> @@ -18,28 +18,31 @@
>  #define MDIO_DATA_WRITE_REG			0x48
>  #define MDIO_DATA_READ_REG			0x4c
>  #define MDIO_CMD_REG				0x50
> -#define MDIO_CMD_ACCESS_BUSY		BIT(16)
> -#define MDIO_CMD_ACCESS_START		BIT(8)
> -#define MDIO_CMD_ACCESS_CODE_READ	0
> -#define MDIO_CMD_ACCESS_CODE_WRITE	1
> -#define MDIO_CMD_ACCESS_CODE_C45_ADDR	0
> -#define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
> -#define MDIO_CMD_ACCESS_CODE_C45_READ	2
> +#define MDIO_CMD_ACCESS_BUSY			BIT(16)
> +#define MDIO_CMD_ACCESS_START			BIT(8)
> +#define MDIO_CMD_ACCESS_CODE_READ		0
> +#define MDIO_CMD_ACCESS_CODE_WRITE		1
> +#define MDIO_CMD_ACCESS_CODE_C45_ADDR		0
> +#define MDIO_CMD_ACCESS_CODE_C45_WRITE		1
> +#define MDIO_CMD_ACCESS_CODE_C45_READ		2

Where is anything related to ipq5332 here?


..

>  	bus->name = "ipq4019_mdio";
>  	bus->read = ipq4019_mdio_read_c22;
> @@ -288,6 +296,7 @@ static void ipq4019_mdio_remove(struct platform_device *pdev)
>  static const struct of_device_id ipq4019_mdio_dt_ids[] = {
>  	{ .compatible = "qcom,ipq4019-mdio" },
>  	{ .compatible = "qcom,ipq5018-mdio" },
> +	{ .compatible = "qcom,ipq5332-mdio" },

How user comes before binding?

Best regards,
Krzysztof
Jie Luo Nov. 17, 2023, 9:56 a.m. UTC | #4 
On 11/16/2023 7:57 PM, Krzysztof Kozlowski wrote:
> On 15/11/2023 04:25, Luo Jie wrote:
>> There are two PCS(UNIPHY) supported in SOC side on ipq5332,
>> and three PCS(UNIPHY) supported on ipq9574.
>>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   drivers/net/mdio/mdio-ipq4019.c | 55 +++++++++++++++++++--------------
>>   1 file changed, 32 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
>> index abd8b508ec16..9d444f5f7efb 100644
>> --- a/drivers/net/mdio/mdio-ipq4019.c
>> +++ b/drivers/net/mdio/mdio-ipq4019.c
>> @@ -18,28 +18,31 @@
>>   #define MDIO_DATA_WRITE_REG			0x48
>>   #define MDIO_DATA_READ_REG			0x4c
>>   #define MDIO_CMD_REG				0x50
>> -#define MDIO_CMD_ACCESS_BUSY		BIT(16)
>> -#define MDIO_CMD_ACCESS_START		BIT(8)
>> -#define MDIO_CMD_ACCESS_CODE_READ	0
>> -#define MDIO_CMD_ACCESS_CODE_WRITE	1
>> -#define MDIO_CMD_ACCESS_CODE_C45_ADDR	0
>> -#define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
>> -#define MDIO_CMD_ACCESS_CODE_C45_READ	2
>> +#define MDIO_CMD_ACCESS_BUSY			BIT(16)
>> +#define MDIO_CMD_ACCESS_START			BIT(8)
>> +#define MDIO_CMD_ACCESS_CODE_READ		0
>> +#define MDIO_CMD_ACCESS_CODE_WRITE		1
>> +#define MDIO_CMD_ACCESS_CODE_C45_ADDR		0
>> +#define MDIO_CMD_ACCESS_CODE_C45_WRITE		1
>> +#define MDIO_CMD_ACCESS_CODE_C45_READ		2
> 
> Where is anything related to ipq5332 here?

This is for alignment format, will keep it untouched in the next
patch set.

> 
> 
> ..
> 
>>   	bus->name = "ipq4019_mdio";
>>   	bus->read = ipq4019_mdio_read_c22;
>> @@ -288,6 +296,7 @@ static void ipq4019_mdio_remove(struct platform_device *pdev)
>>   static const struct of_device_id ipq4019_mdio_dt_ids[] = {
>>   	{ .compatible = "qcom,ipq4019-mdio" },
>>   	{ .compatible = "qcom,ipq5018-mdio" },
>> +	{ .compatible = "qcom,ipq5332-mdio" },
> 
> How user comes before binding?

The new added compatible is for the GCC uniphy AHB/SYS clocks configured
on the ipq5332 platform, will move this change into the following patch
that involves the ipq5332 to make it clear.

<net: mdio: ipq4019: Enable the clocks for ipq5332 platform>.

> 
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c
index abd8b508ec16..9d444f5f7efb 100644
--- a/drivers/net/mdio/mdio-ipq4019.c
+++ b/drivers/net/mdio/mdio-ipq4019.c
@@ -18,28 +18,31 @@ 
 #define MDIO_DATA_WRITE_REG			0x48
 #define MDIO_DATA_READ_REG			0x4c
 #define MDIO_CMD_REG				0x50
-#define MDIO_CMD_ACCESS_BUSY		BIT(16)
-#define MDIO_CMD_ACCESS_START		BIT(8)
-#define MDIO_CMD_ACCESS_CODE_READ	0
-#define MDIO_CMD_ACCESS_CODE_WRITE	1
-#define MDIO_CMD_ACCESS_CODE_C45_ADDR	0
-#define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
-#define MDIO_CMD_ACCESS_CODE_C45_READ	2
+#define MDIO_CMD_ACCESS_BUSY			BIT(16)
+#define MDIO_CMD_ACCESS_START			BIT(8)
+#define MDIO_CMD_ACCESS_CODE_READ		0
+#define MDIO_CMD_ACCESS_CODE_WRITE		1
+#define MDIO_CMD_ACCESS_CODE_C45_ADDR		0
+#define MDIO_CMD_ACCESS_CODE_C45_WRITE		1
+#define MDIO_CMD_ACCESS_CODE_C45_READ		2
 
 /* 0 = Clause 22, 1 = Clause 45 */
 #define MDIO_MODE_C45				BIT(8)
 
-#define IPQ4019_MDIO_TIMEOUT	10000
-#define IPQ4019_MDIO_SLEEP		10
+#define IPQ4019_MDIO_TIMEOUT			10000
+#define IPQ4019_MDIO_SLEEP			10
 
 /* MDIO clock source frequency is fixed to 100M */
-#define IPQ_MDIO_CLK_RATE	100000000
+#define IPQ_MDIO_CLK_RATE			100000000
 
-#define IPQ_PHY_SET_DELAY_US	100000
+#define IPQ_PHY_SET_DELAY_US			100000
+
+/* Maximum SOC PCS(uniphy) number on IPQ platform */
+#define ETH_LDO_RDY_CNT				3
 
 struct ipq4019_mdio_data {
-	void __iomem	*membase;
-	void __iomem *eth_ldo_rdy;
+	void __iomem *membase;
+	void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT];
 	struct clk *mdio_clk;
 };
 
@@ -210,13 +213,15 @@  static int ipq_mdio_reset(struct mii_bus *bus)
 	int ret;
 
 	/* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1
-	 * is specified in the device tree.
+	 * or more resource are specified in the device tree.
 	 */
-	if (priv->eth_ldo_rdy) {
-		val = readl(priv->eth_ldo_rdy);
-		val |= BIT(0);
-		writel(val, priv->eth_ldo_rdy);
-		fsleep(IPQ_PHY_SET_DELAY_US);
+	for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) {
+		if (priv->eth_ldo_rdy[ret]) {
+			val = readl(priv->eth_ldo_rdy[ret]);
+			val |= BIT(0);
+			writel(val, priv->eth_ldo_rdy[ret]);
+			fsleep(IPQ_PHY_SET_DELAY_US);
+		}
 	}
 
 	/* Configure MDIO clock source frequency if clock is specified in the device tree */
@@ -252,11 +257,14 @@  static int ipq4019_mdio_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->mdio_clk))
 		return PTR_ERR(priv->mdio_clk);
 
-	/* The platform resource is provided on the chipset IPQ5018 */
+	/* The platform resource is provided on the chipset IPQ5018/IPQ5332 */
 	/* This resource is optional */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	if (res)
-		priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res);
+	for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, ret + 1);
+		if (res)
+			priv->eth_ldo_rdy[ret] = devm_ioremap(&pdev->dev,
+							      res->start, resource_size(res));
+	}
 
 	bus->name = "ipq4019_mdio";
 	bus->read = ipq4019_mdio_read_c22;
@@ -288,6 +296,7 @@  static void ipq4019_mdio_remove(struct platform_device *pdev)
 static const struct of_device_id ipq4019_mdio_dt_ids[] = {
 	{ .compatible = "qcom,ipq4019-mdio" },
 	{ .compatible = "qcom,ipq5018-mdio" },
+	{ .compatible = "qcom,ipq5332-mdio" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, ipq4019_mdio_dt_ids);