diff mbox series

[v4,01/20] riscv: add ISA extension parsing for Zbc

Message ID	20231114141256.126749-2-cleger@rivosinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Andrew Jones <ajones@ventanamicro.com>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor@kernel.org>, Samuel Ortiz <sameo@rivosinc.com>, Jerry Shih <jerry.shih@sifive.com> Subject: [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Date: Tue, 14 Nov 2023 09:12:37 -0500 Message-ID: <20231114141256.126749-2-cleger@rivosinc.com> In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: report more ISA extensions through hwprobe \| [v4,00/20] riscv: report more ISA extensions through hwprobe [v4,01/20] riscv: add ISA extension parsing for Zbc [v4,02/20] riscv: hwprobe: export missing Zbc ISA extension [v4,03/20] riscv: add ISA extension parsing for scalar crypto [v4,04/20] riscv: hwprobe: add support for scalar crypto ISA extensions [v4,05/20] dt-bindings: riscv: add scalar crypto ISA extensions description [v4,06/20] riscv: add ISA extension parsing for vector crypto [v4,07/20] riscv: hwprobe: export vector crypto ISA extensions [v4,08/20] dt-bindings: riscv: add vector crypto ISA extensions description [v4,09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] [v4,10/20] riscv: hwprobe: export Zfh[min] ISA extensions [v4,11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description [v4,12/20] riscv: add ISA extension parsing for Zihintntl [v4,13/20] riscv: hwprobe: export Zhintntl ISA extension [v4,14/20] dt-bindings: riscv: add Zihintntl ISA extension description [v4,15/20] riscv: add ISA extension parsing for Zvfh[min] [v4,16/20] riscv: hwprobe: export Zvfh[min] ISA extensions [v4,17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description [v4,18/20] riscv: add ISA extension parsing for Zfa [v4,19/20] riscv: hwprobe: export Zfa ISA extension [v4,20/20] dt-bindings: riscv: add Zfa ISA extension description

Commit Message

Clément Léger Nov. 14, 2023, 2:12 p.m. UTC

  Zbc was documented in the dt-bindings but actually not supported in ISA
string parsing. Add it.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 06d30526ef3b..afa9abc1a0b0 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -57,6 +57,7 @@ 
 #define RISCV_ISA_EXT_ZIHPM		42
 #define RISCV_ISA_EXT_SMSTATEEN		43
 #define RISCV_ISA_EXT_ZICOND		44
+#define RISCV_ISA_EXT_ZBC		45
 
 #define RISCV_ISA_EXT_MAX		64
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b3785ffc1570..eae14daa5a75 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -176,6 +176,7 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
+	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
 	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),