Message ID | 20231109-th1520-mmc-v5-4-018bd039cf17@baylibre.com |
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State | New |
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Thu, 09 Nov 2023 21:42:32 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:32 -0800 (PST) From: Drew Fustini <dfustini@baylibre.com> Date: Thu, 09 Nov 2023 21:41:14 -0800 Subject: [PATCH v5 4/7] riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20231109-th1520-mmc-v5-4-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Jisheng Zhang <jszhang@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, Conor Dooley <conor@kernel.org> Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini <dfustini@baylibre.com> X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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RISC-V: Add MMC support for TH1520 boards
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Commit Message
Drew Fustini
Nov. 10, 2023, 5:41 a.m. UTC
Enable the mmc controller driver and dma controller driver needed for T-Head TH1520 based boards, like the LicheePi 4A and BeagleV-Ahead, to boot from eMMC storage. Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Drew Fustini <dfustini@baylibre.com> --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..c5a8583236d0 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -168,12 +168,14 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SPI=y CONFIG_MMC_SUNXI=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SUN6I=y CONFIG_DMADEVICES=y CONFIG_DMA_SUN6I=m +CONFIG_DW_AXI_DMAC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y