Message ID | 20231104000239.367005-10-seanjc@google.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp1379448vqu; Fri, 3 Nov 2023 17:03:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHfk5a8vCYRQ0Z/t5CoQRCqW/VVQholN3nkg7rtn1RxN7ZqBZTtDAMRxERr9aFBmeegoZ+t X-Received: by 2002:a92:cdaf:0:b0:357:600c:7c5f with SMTP id g15-20020a92cdaf000000b00357600c7c5fmr28367464ild.23.1699056200885; Fri, 03 Nov 2023 17:03:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1699056200; cv=none; d=google.com; s=arc-20160816; b=Qvq2pOiR9S9UWH9a5PF474hMn03Bvc7SHpu2Uwqy0YmGH45tst9B9UdnOpM8UbM99d Y4sRwt5nFMRQmgyc0uQCZCCdmpnD3JSdtgekeZt+bDkcXVIuJDCekEkv3TlL60JnxVd4 tzlwftXG5NaV2FUkSV+E8VtHeVQfck96r5O0hCeAtyw4gEdl907KdOsg0aiaxQP1ZEa4 vzbUukaVbmolCmvW9jaZsDB4k73PlVUwY1qEGKBABFN87d6es6e9lRh+FbMKVPMBmlDI XgOyM4dv/uIfYrigDqnyjLNgkidohux8x4xUQurnHHyevx7hJ9OoMLLuuIx/tjzBbCxY nuZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:reply-to:dkim-signature; bh=1N0GaX165iT66psQLFguu13B6wTdKAbnF/+ecMums54=; fh=z/UQYx9FUD9Bz9JyYrmi2ijAScp29gktKr8lejSUuXU=; b=rKeEBVc3GMgwwSsVWGMPRaVR/Go+m1NhVkjwHX+sPuHVIGO9awkG8Pmssx/BAsmFPw vNNIZcxvyowYs93ZfUiqRzT0N4SHfO1uyyrMNGlW4h/YAUjBePH5eNz712GC4KFwN1aJ P0AcsIeOKgfJ0tvMWZb1YPYjqGqyX4WI19wMm7mmuThRSYlQrzcg3A1l3lcv9eak+8tB YmLN4/h435YS9PqIle9HM301Yk0wqLPmXdfO1z9BiJ1PWRe5Qrebo9er3wYVhBdBdAby cAj3Kiex68dnDQjVHx2UBvJcMu73JdAigwq0O+7Jhj3P4bjN4xAounotawXFQ+PZhF2F sR0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=2JNsa86Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id bs67-20020a632846000000b005b9968392e6si2399125pgb.430.2023.11.03.17.03.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 17:03:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20230601 header.b=2JNsa86Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 0EC4181398B8; Fri, 3 Nov 2023 17:03:19 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231826AbjKDADN (ORCPT <rfc822;heyuhang3455@gmail.com> + 35 others); Fri, 3 Nov 2023 20:03:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231629AbjKDADG (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 3 Nov 2023 20:03:06 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFC1AE5 for <linux-kernel@vger.kernel.org>; Fri, 3 Nov 2023 17:02:58 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-da0631f977bso3121372276.2 for <linux-kernel@vger.kernel.org>; Fri, 03 Nov 2023 17:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056178; x=1699660978; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=1N0GaX165iT66psQLFguu13B6wTdKAbnF/+ecMums54=; b=2JNsa86YjKyGvL7VYfvUYmADES12Vl+vE8WEhrOQCHLeyxnf4+Vv/ohEifudVQmAzO z9WsetlRVUKMg/IxzWbwU/VCnl+nG2Ykl6p766WnbV6BBmjxp2Do3/btuxnL/GkdbUsc xnkCdyHPs7AzYSWuVQyEeIarYXusr9XBL5iWXx5Cfrvu/IpaYSiMNEhm8xcoJnyhAVLn VUOWIfaj2V5O0ZIZmVWkWDFe9dY7iuKppsGgUTi1IfP8TPvjczp03qbgN4Gb/dHZlNAD U6bv5APthuzZ2A6fD0MiMtrQowfDq6vIOxQSDtG2/gaCmYftRQQcuRcKeH39GhLIRmCF zZqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056178; x=1699660978; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1N0GaX165iT66psQLFguu13B6wTdKAbnF/+ecMums54=; b=r+BRf8vDTeCiAqkhG8KkKE9iro3kNk5PjXOjwo96FJ3J5sg6Lns37BnE1KP5+bj6gK nwdCeekZ13U5bJVgFWNdk1vYOz5H1WJxxBia1mv/eG2wtXm3PimeDUazPoz2HNXKuOGi Qd3BIePmtgd0dV+ZoshglBCOcJM1K0NqERcqDRsd8xQIO+moPt+SzqLclmHpMteGAlmm YKpE3C8Dnw+b5/Ma9Nr4XKq6O0oFa6NC3z9mlQbmlFMl1C2mP2E/fnyu/zkT994oIqmD Vv39C/WGtKVauXfhM3ST2PAWQo/gQj48KbglqDZd3sTMNwu/hQwQiXcyEwLUP0pHg3gG 0fBg== X-Gm-Message-State: AOJu0YxgFN8Qi1OjrK7+D54sfrZes9qSHgVyuJF3aJfSHSu6N05c2ZOg UEETc1/tyKtkmR8KMuiwltlUCUSBjrs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:5c2:0:b0:d9a:68de:16a1 with SMTP id 185-20020a2505c2000000b00d9a68de16a1mr458880ybf.0.1699056178051; Fri, 03 Nov 2023 17:02:58 -0700 (PDT) Reply-To: Sean Christopherson <seanjc@google.com> Date: Fri, 3 Nov 2023 17:02:27 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-10-seanjc@google.com> Subject: [PATCH v6 09/20] KVM: selftests: Add pmu.h and lib/pmu.c for common PMU assets From: Sean Christopherson <seanjc@google.com> To: Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang <kan.liang@linux.intel.com>, Dapeng Mi <dapeng1.mi@linux.intel.com>, Jinrong Liang <cloudliang@tencent.com>, Like Xu <likexu@tencent.com>, Jim Mattson <jmattson@google.com>, Aaron Lewis <aaronlewis@google.com> Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 03 Nov 2023 17:03:20 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781589554722081266 X-GMAIL-MSGID: 1781589554722081266 |
Series |
KVM: x86/pmu: selftests: Fixes and new tests
|
|
Commit Message
Sean Christopherson
Nov. 4, 2023, 12:02 a.m. UTC
From: Jinrong Liang <cloudliang@tencent.com> By defining the PMU performance events and masks relevant for x86 in the new pmu.h and pmu.c, it becomes easier to reference them, minimizing potential errors in code that handles these values. Clean up pmu_event_filter_test.c by including pmu.h and removing unnecessary macros. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Jinrong Liang <cloudliang@tencent.com> [sean: drop PSEUDO_ARCH_REFERENCE_CYCLES] Signed-off-by: Sean Christopherson <seanjc@google.com> --- tools/testing/selftests/kvm/Makefile | 1 + tools/testing/selftests/kvm/include/pmu.h | 84 +++++++++++++++++++ tools/testing/selftests/kvm/lib/pmu.c | 28 +++++++ .../kvm/x86_64/pmu_event_filter_test.c | 32 ++----- 4 files changed, 122 insertions(+), 23 deletions(-) create mode 100644 tools/testing/selftests/kvm/include/pmu.h create mode 100644 tools/testing/selftests/kvm/lib/pmu.c
Comments
On Fri, Nov 3, 2023 at 5:02 PM Sean Christopherson <seanjc@google.com> wrote: > > From: Jinrong Liang <cloudliang@tencent.com> > > By defining the PMU performance events and masks relevant for x86 in > the new pmu.h and pmu.c, it becomes easier to reference them, minimizing > potential errors in code that handles these values. > > Clean up pmu_event_filter_test.c by including pmu.h and removing > unnecessary macros. > > Suggested-by: Sean Christopherson <seanjc@google.com> > Signed-off-by: Jinrong Liang <cloudliang@tencent.com> > [sean: drop PSEUDO_ARCH_REFERENCE_CYCLES] > Signed-off-by: Sean Christopherson <seanjc@google.com> > --- > tools/testing/selftests/kvm/Makefile | 1 + > tools/testing/selftests/kvm/include/pmu.h | 84 +++++++++++++++++++ > tools/testing/selftests/kvm/lib/pmu.c | 28 +++++++ > .../kvm/x86_64/pmu_event_filter_test.c | 32 ++----- > 4 files changed, 122 insertions(+), 23 deletions(-) > create mode 100644 tools/testing/selftests/kvm/include/pmu.h > create mode 100644 tools/testing/selftests/kvm/lib/pmu.c > > diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile > index a5963ab9215b..44d8d022b023 100644 > --- a/tools/testing/selftests/kvm/Makefile > +++ b/tools/testing/selftests/kvm/Makefile > @@ -32,6 +32,7 @@ LIBKVM += lib/guest_modes.c > LIBKVM += lib/io.c > LIBKVM += lib/kvm_util.c > LIBKVM += lib/memstress.c > +LIBKVM += lib/pmu.c > LIBKVM += lib/guest_sprintf.c > LIBKVM += lib/rbtree.c > LIBKVM += lib/sparsebit.c > diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/selftests/kvm/include/pmu.h > new file mode 100644 > index 000000000000..987602c62b51 > --- /dev/null > +++ b/tools/testing/selftests/kvm/include/pmu.h > @@ -0,0 +1,84 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2023, Tencent, Inc. > + */ > +#ifndef SELFTEST_KVM_PMU_H > +#define SELFTEST_KVM_PMU_H > + > +#include <stdint.h> > + > +#define X86_PMC_IDX_MAX 64 > +#define INTEL_PMC_MAX_GENERIC 32 I think this is actually 15. Note that IA32_PMC0 through IA32_PMC7 have MSR indices from 0xc1 through 0xc8, and MSR 0xcf is IA32_CORE_CAPABILITIES. At the very least, we have to handle non-contiguous MSR indices if we ever go beyond IA32_PMC14. > +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 > + > +#define GP_COUNTER_NR_OFS_BIT 8 > +#define EVENT_LENGTH_OFS_BIT 24 > + > +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) > +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) > +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) > +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) > + > +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) > +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) > +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) > +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) > +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) > +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) > +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) > +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) > +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) > +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) > +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) > + > +#define PMC_MAX_FIXED 16 > +#define PMC_IDX_FIXED 32 > + > +/* RDPMC offset for Fixed PMCs */ > +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) > +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) > + > +#define FIXED_BITS_MASK 0xFULL > +#define FIXED_BITS_STRIDE 4 > +#define FIXED_0_KERNEL BIT_ULL(0) > +#define FIXED_0_USER BIT_ULL(1) > +#define FIXED_0_ANYTHREAD BIT_ULL(2) > +#define FIXED_0_ENABLE_PMI BIT_ULL(3) > + > +#define fixed_bits_by_idx(_idx, _bits) \ > + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) > + > +#define AMD64_NR_COUNTERS 4 > +#define AMD64_NR_COUNTERS_CORE 6 > + > +#define PMU_CAP_FW_WRITES BIT_ULL(13) > +#define PMU_CAP_LBR_FMT 0x3f > + > +enum intel_pmu_architectural_events { > + /* > + * The order of the architectural events matters as support for each > + * event is enumerated via CPUID using the index of the event. > + */ > + INTEL_ARCH_CPU_CYCLES, > + INTEL_ARCH_INSTRUCTIONS_RETIRED, > + INTEL_ARCH_REFERENCE_CYCLES, > + INTEL_ARCH_LLC_REFERENCES, > + INTEL_ARCH_LLC_MISSES, > + INTEL_ARCH_BRANCHES_RETIRED, > + INTEL_ARCH_BRANCHES_MISPREDICTED, > + NR_INTEL_ARCH_EVENTS, > +}; > + > +enum amd_pmu_k7_events { > + AMD_ZEN_CORE_CYCLES, > + AMD_ZEN_INSTRUCTIONS, > + AMD_ZEN_BRANCHES, > + AMD_ZEN_BRANCH_MISSES, > + NR_AMD_ARCH_EVENTS, > +}; > + > +extern const uint64_t intel_pmu_arch_events[]; > +extern const uint64_t amd_pmu_arch_events[]; AMD doesn't define *any* architectural events. Perhaps amd_pmu_zen_events[], though who knows what Zen5 and beyond will bring? > +extern const int intel_pmu_fixed_pmc_events[]; > + > +#endif /* SELFTEST_KVM_PMU_H */ > diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftests/kvm/lib/pmu.c > new file mode 100644 > index 000000000000..27a6c35f98a1 > --- /dev/null > +++ b/tools/testing/selftests/kvm/lib/pmu.c > @@ -0,0 +1,28 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023, Tencent, Inc. > + */ > + > +#include <stdint.h> > + > +#include "pmu.h" > + > +/* Definitions for Architectural Performance Events */ > +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) There's nothing architectural about this. Perhaps RAW_EVENT() for consistency with perf? > + > +const uint64_t intel_pmu_arch_events[] = { > + [INTEL_ARCH_CPU_CYCLES] = ARCH_EVENT(0x3c, 0x0), > + [INTEL_ARCH_INSTRUCTIONS_RETIRED] = ARCH_EVENT(0xc0, 0x0), > + [INTEL_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0x3c, 0x1), > + [INTEL_ARCH_LLC_REFERENCES] = ARCH_EVENT(0x2e, 0x4f), > + [INTEL_ARCH_LLC_MISSES] = ARCH_EVENT(0x2e, 0x41), > + [INTEL_ARCH_BRANCHES_RETIRED] = ARCH_EVENT(0xc4, 0x0), > + [INTEL_ARCH_BRANCHES_MISPREDICTED] = ARCH_EVENT(0xc5, 0x0), [INTEL_ARCH_TOPDOWN_SLOTS] = ARCH_EVENT(0xa4, 1), > +}; > + > +const uint64_t amd_pmu_arch_events[] = { > + [AMD_ZEN_CORE_CYCLES] = ARCH_EVENT(0x76, 0x00), > + [AMD_ZEN_INSTRUCTIONS] = ARCH_EVENT(0xc0, 0x00), > + [AMD_ZEN_BRANCHES] = ARCH_EVENT(0xc2, 0x00), > + [AMD_ZEN_BRANCH_MISSES] = ARCH_EVENT(0xc3, 0x00), > +}; > diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c > index 283cc55597a4..b6e4f57a8651 100644 > --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c > +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c > @@ -11,31 +11,18 @@ > */ > > #define _GNU_SOURCE /* for program_invocation_short_name */ > -#include "test_util.h" > + > #include "kvm_util.h" > +#include "pmu.h" > #include "processor.h" > - > -/* > - * In lieu of copying perf_event.h into tools... > - */ > -#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) > -#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) > - > -/* End of stuff taken from perf_event.h. */ > - > -/* Oddly, this isn't in perf_event.h. */ > -#define ARCH_PERFMON_BRANCHES_RETIRED 5 > +#include "test_util.h" > > #define NUM_BRANCHES 42 > -#define INTEL_PMC_IDX_FIXED 32 > - > -/* Matches KVM_PMU_EVENT_FILTER_MAX_EVENTS in pmu.c */ > -#define MAX_FILTER_EVENTS 300 > #define MAX_TEST_EVENTS 10 > > #define PMU_EVENT_FILTER_INVALID_ACTION (KVM_PMU_EVENT_DENY + 1) > #define PMU_EVENT_FILTER_INVALID_FLAGS (KVM_PMU_EVENT_FLAGS_VALID_MASK << 1) > -#define PMU_EVENT_FILTER_INVALID_NEVENTS (MAX_FILTER_EVENTS + 1) > +#define PMU_EVENT_FILTER_INVALID_NEVENTS (KVM_PMU_EVENT_FILTER_MAX_EVENTS + 1) > > /* > * This is how the event selector and unit mask are stored in an AMD > @@ -63,7 +50,6 @@ > > #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) Now AMD_ZEN_BRANCHES, above? > > - > /* > * "Retired instructions", from Processor Programming Reference > * (PPR) for AMD Family 17h Model 01h, Revision B1 Processors, > @@ -84,7 +70,7 @@ struct __kvm_pmu_event_filter { > __u32 fixed_counter_bitmap; > __u32 flags; > __u32 pad[4]; > - __u64 events[MAX_FILTER_EVENTS]; > + __u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; > }; > > /* > @@ -729,14 +715,14 @@ static void add_dummy_events(uint64_t *events, int nevents) > > static void test_masked_events(struct kvm_vcpu *vcpu) > { > - int nevents = MAX_FILTER_EVENTS - MAX_TEST_EVENTS; > - uint64_t events[MAX_FILTER_EVENTS]; > + int nevents = KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS; > + uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; > > /* Run the test cases against a sparse PMU event filter. */ > run_masked_events_tests(vcpu, events, 0); > > /* Run the test cases against a dense PMU event filter. */ > - add_dummy_events(events, MAX_FILTER_EVENTS); > + add_dummy_events(events, KVM_PMU_EVENT_FILTER_MAX_EVENTS); > run_masked_events_tests(vcpu, events, nevents); > } > > @@ -818,7 +804,7 @@ static void intel_run_fixed_counter_guest_code(uint8_t fixed_ctr_idx) > /* Only OS_EN bit is enabled for fixed counter[idx]. */ > wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * fixed_ctr_idx)); > wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, > - BIT_ULL(INTEL_PMC_IDX_FIXED + fixed_ctr_idx)); > + BIT_ULL(PMC_IDX_FIXED + fixed_ctr_idx)); > __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); > wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); > > -- > 2.42.0.869.gea05f2083d-goog >
在 2023/11/4 21:20, Jim Mattson 写道: > On Fri, Nov 3, 2023 at 5:02 PM Sean Christopherson <seanjc@google.com> wrote: >> >> From: Jinrong Liang <cloudliang@tencent.com> >> >> By defining the PMU performance events and masks relevant for x86 in >> the new pmu.h and pmu.c, it becomes easier to reference them, minimizing >> potential errors in code that handles these values. >> >> Clean up pmu_event_filter_test.c by including pmu.h and removing >> unnecessary macros. >> >> Suggested-by: Sean Christopherson <seanjc@google.com> >> Signed-off-by: Jinrong Liang <cloudliang@tencent.com> >> [sean: drop PSEUDO_ARCH_REFERENCE_CYCLES] >> Signed-off-by: Sean Christopherson <seanjc@google.com> >> --- >> tools/testing/selftests/kvm/Makefile | 1 + >> tools/testing/selftests/kvm/include/pmu.h | 84 +++++++++++++++++++ >> tools/testing/selftests/kvm/lib/pmu.c | 28 +++++++ >> .../kvm/x86_64/pmu_event_filter_test.c | 32 ++----- >> 4 files changed, 122 insertions(+), 23 deletions(-) >> create mode 100644 tools/testing/selftests/kvm/include/pmu.h >> create mode 100644 tools/testing/selftests/kvm/lib/pmu.c >> >> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile >> index a5963ab9215b..44d8d022b023 100644 >> --- a/tools/testing/selftests/kvm/Makefile >> +++ b/tools/testing/selftests/kvm/Makefile >> @@ -32,6 +32,7 @@ LIBKVM += lib/guest_modes.c >> LIBKVM += lib/io.c >> LIBKVM += lib/kvm_util.c >> LIBKVM += lib/memstress.c >> +LIBKVM += lib/pmu.c >> LIBKVM += lib/guest_sprintf.c >> LIBKVM += lib/rbtree.c >> LIBKVM += lib/sparsebit.c >> diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/selftests/kvm/include/pmu.h >> new file mode 100644 >> index 000000000000..987602c62b51 >> --- /dev/null >> +++ b/tools/testing/selftests/kvm/include/pmu.h >> @@ -0,0 +1,84 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> +/* >> + * Copyright (C) 2023, Tencent, Inc. >> + */ >> +#ifndef SELFTEST_KVM_PMU_H >> +#define SELFTEST_KVM_PMU_H >> + >> +#include <stdint.h> >> + >> +#define X86_PMC_IDX_MAX 64 >> +#define INTEL_PMC_MAX_GENERIC 32 > > I think this is actually 15. Note that IA32_PMC0 through IA32_PMC7 > have MSR indices from 0xc1 through 0xc8, and MSR 0xcf is > IA32_CORE_CAPABILITIES. At the very least, we have to handle > non-contiguous MSR indices if we ever go beyond IA32_PMC14. > >> +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 >> + >> +#define GP_COUNTER_NR_OFS_BIT 8 >> +#define EVENT_LENGTH_OFS_BIT 24 >> + >> +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) >> +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) >> +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) >> +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) >> + >> +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) >> +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) >> +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) >> +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) >> +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) >> +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) >> +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) >> +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) >> +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) >> +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) >> +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) >> + >> +#define PMC_MAX_FIXED 16 >> +#define PMC_IDX_FIXED 32 >> + >> +/* RDPMC offset for Fixed PMCs */ >> +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) >> +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) >> + >> +#define FIXED_BITS_MASK 0xFULL >> +#define FIXED_BITS_STRIDE 4 >> +#define FIXED_0_KERNEL BIT_ULL(0) >> +#define FIXED_0_USER BIT_ULL(1) >> +#define FIXED_0_ANYTHREAD BIT_ULL(2) >> +#define FIXED_0_ENABLE_PMI BIT_ULL(3) >> + >> +#define fixed_bits_by_idx(_idx, _bits) \ >> + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) >> + >> +#define AMD64_NR_COUNTERS 4 >> +#define AMD64_NR_COUNTERS_CORE 6 >> + >> +#define PMU_CAP_FW_WRITES BIT_ULL(13) >> +#define PMU_CAP_LBR_FMT 0x3f >> + >> +enum intel_pmu_architectural_events { >> + /* >> + * The order of the architectural events matters as support for each >> + * event is enumerated via CPUID using the index of the event. >> + */ >> + INTEL_ARCH_CPU_CYCLES, >> + INTEL_ARCH_INSTRUCTIONS_RETIRED, >> + INTEL_ARCH_REFERENCE_CYCLES, >> + INTEL_ARCH_LLC_REFERENCES, >> + INTEL_ARCH_LLC_MISSES, >> + INTEL_ARCH_BRANCHES_RETIRED, >> + INTEL_ARCH_BRANCHES_MISPREDICTED, >> + NR_INTEL_ARCH_EVENTS, >> +}; >> + >> +enum amd_pmu_k7_events { >> + AMD_ZEN_CORE_CYCLES, >> + AMD_ZEN_INSTRUCTIONS, >> + AMD_ZEN_BRANCHES, >> + AMD_ZEN_BRANCH_MISSES, >> + NR_AMD_ARCH_EVENTS, >> +}; >> + >> +extern const uint64_t intel_pmu_arch_events[]; >> +extern const uint64_t amd_pmu_arch_events[]; > > AMD doesn't define *any* architectural events. Perhaps > amd_pmu_zen_events[], though who knows what Zen5 and beyond will > bring? > >> +extern const int intel_pmu_fixed_pmc_events[]; >> + >> +#endif /* SELFTEST_KVM_PMU_H */ >> diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftests/kvm/lib/pmu.c >> new file mode 100644 >> index 000000000000..27a6c35f98a1 >> --- /dev/null >> +++ b/tools/testing/selftests/kvm/lib/pmu.c >> @@ -0,0 +1,28 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2023, Tencent, Inc. >> + */ >> + >> +#include <stdint.h> >> + >> +#include "pmu.h" >> + >> +/* Definitions for Architectural Performance Events */ >> +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) > > There's nothing architectural about this. Perhaps RAW_EVENT() for > consistency with perf? > >> + >> +const uint64_t intel_pmu_arch_events[] = { >> + [INTEL_ARCH_CPU_CYCLES] = ARCH_EVENT(0x3c, 0x0), >> + [INTEL_ARCH_INSTRUCTIONS_RETIRED] = ARCH_EVENT(0xc0, 0x0), >> + [INTEL_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0x3c, 0x1), >> + [INTEL_ARCH_LLC_REFERENCES] = ARCH_EVENT(0x2e, 0x4f), >> + [INTEL_ARCH_LLC_MISSES] = ARCH_EVENT(0x2e, 0x41), >> + [INTEL_ARCH_BRANCHES_RETIRED] = ARCH_EVENT(0xc4, 0x0), >> + [INTEL_ARCH_BRANCHES_MISPREDICTED] = ARCH_EVENT(0xc5, 0x0), > > [INTEL_ARCH_TOPDOWN_SLOTS] = ARCH_EVENT(0xa4, 1), > >> +}; >> + >> +const uint64_t amd_pmu_arch_events[] = { >> + [AMD_ZEN_CORE_CYCLES] = ARCH_EVENT(0x76, 0x00), >> + [AMD_ZEN_INSTRUCTIONS] = ARCH_EVENT(0xc0, 0x00), >> + [AMD_ZEN_BRANCHES] = ARCH_EVENT(0xc2, 0x00), >> + [AMD_ZEN_BRANCH_MISSES] = ARCH_EVENT(0xc3, 0x00), >> +}; >> diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c >> index 283cc55597a4..b6e4f57a8651 100644 >> --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c >> +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c >> @@ -11,31 +11,18 @@ >> */ >> >> #define _GNU_SOURCE /* for program_invocation_short_name */ >> -#include "test_util.h" >> + >> #include "kvm_util.h" >> +#include "pmu.h" >> #include "processor.h" >> - >> -/* >> - * In lieu of copying perf_event.h into tools... >> - */ >> -#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) >> -#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) >> - >> -/* End of stuff taken from perf_event.h. */ >> - >> -/* Oddly, this isn't in perf_event.h. */ >> -#define ARCH_PERFMON_BRANCHES_RETIRED 5 >> +#include "test_util.h" >> >> #define NUM_BRANCHES 42 >> -#define INTEL_PMC_IDX_FIXED 32 >> - >> -/* Matches KVM_PMU_EVENT_FILTER_MAX_EVENTS in pmu.c */ >> -#define MAX_FILTER_EVENTS 300 >> #define MAX_TEST_EVENTS 10 >> >> #define PMU_EVENT_FILTER_INVALID_ACTION (KVM_PMU_EVENT_DENY + 1) >> #define PMU_EVENT_FILTER_INVALID_FLAGS (KVM_PMU_EVENT_FLAGS_VALID_MASK << 1) >> -#define PMU_EVENT_FILTER_INVALID_NEVENTS (MAX_FILTER_EVENTS + 1) >> +#define PMU_EVENT_FILTER_INVALID_NEVENTS (KVM_PMU_EVENT_FILTER_MAX_EVENTS + 1) >> >> /* >> * This is how the event selector and unit mask are stored in an AMD >> @@ -63,7 +50,6 @@ >> >> #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) > > Now AMD_ZEN_BRANCHES, above? Yes, I forgot to replace INTEL_BR_RETIRED, AMD_ZEN_BR_RETIRED and INST_RETIRED in pmu_event_filter_test.c and remove their macro definitions. Thanks, Jinrong > >> >> - >> /* >> * "Retired instructions", from Processor Programming Reference >> * (PPR) for AMD Family 17h Model 01h, Revision B1 Processors, >> @@ -84,7 +70,7 @@ struct __kvm_pmu_event_filter { >> __u32 fixed_counter_bitmap; >> __u32 flags; >> __u32 pad[4]; >> - __u64 events[MAX_FILTER_EVENTS]; >> + __u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; >> }; >> >> /* >> @@ -729,14 +715,14 @@ static void add_dummy_events(uint64_t *events, int nevents) >> >> static void test_masked_events(struct kvm_vcpu *vcpu) >> { >> - int nevents = MAX_FILTER_EVENTS - MAX_TEST_EVENTS; >> - uint64_t events[MAX_FILTER_EVENTS]; >> + int nevents = KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS; >> + uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; >> >> /* Run the test cases against a sparse PMU event filter. */ >> run_masked_events_tests(vcpu, events, 0); >> >> /* Run the test cases against a dense PMU event filter. */ >> - add_dummy_events(events, MAX_FILTER_EVENTS); >> + add_dummy_events(events, KVM_PMU_EVENT_FILTER_MAX_EVENTS); >> run_masked_events_tests(vcpu, events, nevents); >> } >> >> @@ -818,7 +804,7 @@ static void intel_run_fixed_counter_guest_code(uint8_t fixed_ctr_idx) >> /* Only OS_EN bit is enabled for fixed counter[idx]. */ >> wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * fixed_ctr_idx)); >> wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, >> - BIT_ULL(INTEL_PMC_IDX_FIXED + fixed_ctr_idx)); >> + BIT_ULL(PMC_IDX_FIXED + fixed_ctr_idx)); >> __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); >> wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); >> >> -- >> 2.42.0.869.gea05f2083d-goog >>
On Mon, Nov 06, 2023, JinrongLiang wrote: > 在 2023/11/4 21:20, Jim Mattson 写道: > > > diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/selftests/kvm/include/pmu.h > > > new file mode 100644 > > > index 000000000000..987602c62b51 > > > --- /dev/null > > > +++ b/tools/testing/selftests/kvm/include/pmu.h > > > @@ -0,0 +1,84 @@ > > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > > +/* > > > + * Copyright (C) 2023, Tencent, Inc. > > > + */ > > > +#ifndef SELFTEST_KVM_PMU_H > > > +#define SELFTEST_KVM_PMU_H > > > + > > > +#include <stdint.h> > > > + > > > +#define X86_PMC_IDX_MAX 64 > > > +#define INTEL_PMC_MAX_GENERIC 32 > > > > I think this is actually 15. Note that IA32_PMC0 through IA32_PMC7 > > have MSR indices from 0xc1 through 0xc8, and MSR 0xcf is > > IA32_CORE_CAPABILITIES. At the very least, we have to handle > > non-contiguous MSR indices if we ever go beyond IA32_PMC14. There's no reason to define this, it's not used in selftests. > > > +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 > > > + > > > +#define GP_COUNTER_NR_OFS_BIT 8 > > > +#define EVENT_LENGTH_OFS_BIT 24 > > > + > > > +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) > > > +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) > > > +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) > > > +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) These are also unneeded, they're superseded by CPUID properties. > > > +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) > > > +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) > > > +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) > > > +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) > > > +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) > > > +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) > > > +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) > > > +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) > > > +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) > > > +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) > > > +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) > > > + > > > +#define PMC_MAX_FIXED 16 Also unneeded. > > > +#define PMC_IDX_FIXED 32 This one is absolutely ridiculous. It's the shift for the enable bit in global control, which is super obvious from the name. /s > > > + > > > +/* RDPMC offset for Fixed PMCs */ > > > +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) > > > +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) > > > + > > > +#define FIXED_BITS_MASK 0xFULL > > > +#define FIXED_BITS_STRIDE 4 > > > +#define FIXED_0_KERNEL BIT_ULL(0) > > > +#define FIXED_0_USER BIT_ULL(1) > > > +#define FIXED_0_ANYTHREAD BIT_ULL(2) > > > +#define FIXED_0_ENABLE_PMI BIT_ULL(3) > > > + > > > +#define fixed_bits_by_idx(_idx, _bits) \ > > > + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) *sigh* And now I see where the "i * 4" stuff in the new test comes from. My plan is to redo the above as: /* RDPMC offset for Fixed PMCs */ #define FIXED_PMC_RDPMC_METRICS BIT_ULL(29) #define FIXED_PMC_RDPMC_BASE BIT_ULL(30) #define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx))) #define FIXED_PMC_KERNEL BIT_ULL(0) #define FIXED_PMC_USER BIT_ULL(1) #define FIXED_PMC_ANYTHREAD BIT_ULL(2) #define FIXED_PMC_ENABLE_PMI BIT_ULL(3) #define FIXED_PMC_NR_BITS 4 #define FIXED_PMC_CTRL(_idx, _val) ((_val) << ((_idx) * FIXED_PMC_NR_BITS)) > > > +#define AMD64_NR_COUNTERS 4 > > > +#define AMD64_NR_COUNTERS_CORE 6 These too can be dropped for now. > > > +#define PMU_CAP_FW_WRITES BIT_ULL(13) > > > +#define PMU_CAP_LBR_FMT 0x3f > > > + > > > +enum intel_pmu_architectural_events { > > > + /* > > > + * The order of the architectural events matters as support for each > > > + * event is enumerated via CPUID using the index of the event. > > > + */ > > > + INTEL_ARCH_CPU_CYCLES, > > > + INTEL_ARCH_INSTRUCTIONS_RETIRED, > > > + INTEL_ARCH_REFERENCE_CYCLES, > > > + INTEL_ARCH_LLC_REFERENCES, > > > + INTEL_ARCH_LLC_MISSES, > > > + INTEL_ARCH_BRANCHES_RETIRED, > > > + INTEL_ARCH_BRANCHES_MISPREDICTED, > > > + NR_INTEL_ARCH_EVENTS, > > > +}; > > > + > > > +enum amd_pmu_k7_events { > > > + AMD_ZEN_CORE_CYCLES, > > > + AMD_ZEN_INSTRUCTIONS, > > > + AMD_ZEN_BRANCHES, > > > + AMD_ZEN_BRANCH_MISSES, > > > + NR_AMD_ARCH_EVENTS, > > > +}; > > > + > > > +extern const uint64_t intel_pmu_arch_events[]; > > > +extern const uint64_t amd_pmu_arch_events[]; > > > > AMD doesn't define *any* architectural events. Perhaps > > amd_pmu_zen_events[], though who knows what Zen5 and beyond will > > bring? > > > > > +extern const int intel_pmu_fixed_pmc_events[]; > > > + > > > +#endif /* SELFTEST_KVM_PMU_H */ > > > diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftests/kvm/lib/pmu.c > > > new file mode 100644 > > > index 000000000000..27a6c35f98a1 > > > --- /dev/null > > > +++ b/tools/testing/selftests/kvm/lib/pmu.c > > > @@ -0,0 +1,28 @@ > > > +// SPDX-License-Identifier: GPL-2.0-only > > > +/* > > > + * Copyright (C) 2023, Tencent, Inc. > > > + */ > > > + > > > +#include <stdint.h> > > > + > > > +#include "pmu.h" > > > + > > > +/* Definitions for Architectural Performance Events */ > > > +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) > > > > There's nothing architectural about this. Perhaps RAW_EVENT() for > > consistency with perf? Works for me. > > > +const uint64_t intel_pmu_arch_events[] = { > > > + [INTEL_ARCH_CPU_CYCLES] = ARCH_EVENT(0x3c, 0x0), > > > + [INTEL_ARCH_INSTRUCTIONS_RETIRED] = ARCH_EVENT(0xc0, 0x0), > > > + [INTEL_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0x3c, 0x1), > > > + [INTEL_ARCH_LLC_REFERENCES] = ARCH_EVENT(0x2e, 0x4f), > > > + [INTEL_ARCH_LLC_MISSES] = ARCH_EVENT(0x2e, 0x41), > > > + [INTEL_ARCH_BRANCHES_RETIRED] = ARCH_EVENT(0xc4, 0x0), > > > + [INTEL_ARCH_BRANCHES_MISPREDICTED] = ARCH_EVENT(0xc5, 0x0), > > > > [INTEL_ARCH_TOPDOWN_SLOTS] = ARCH_EVENT(0xa4, 1), ... > > > @@ -63,7 +50,6 @@ > > > > > > #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) > > > > Now AMD_ZEN_BRANCHES, above? > > Yes, I forgot to replace INTEL_BR_RETIRED, AMD_ZEN_BR_RETIRED and > INST_RETIRED in pmu_event_filter_test.c and remove their macro definitions. Having to go through an array to get a hardcoded value is silly, e.g. it makes it unnecessarily difficult to reference the encodings because they aren't simple literals. My vote is this: #define INTEL_ARCH_CPU_CYCLES RAW_EVENT(0x3c, 0x00) #define INTEL_ARCH_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00) #define INTEL_ARCH_REFERENCE_CYCLES RAW_EVENT(0x3c, 0x01) #define INTEL_ARCH_LLC_REFERENCES RAW_EVENT(0x2e, 0x4f) #define INTEL_ARCH_LLC_MISSES RAW_EVENT(0x2e, 0x41) #define INTEL_ARCH_BRANCHES_RETIRED RAW_EVENT(0xc4, 0x00) #define INTEL_ARCH_BRANCHES_MISPREDICTED RAW_EVENT(0xc5, 0x00) #define INTEL_ARCH_TOPDOWN_SLOTS RAW_EVENT(0xa4, 0x01) #define AMD_ZEN_CORE_CYCLES RAW_EVENT(0x76, 0x00) #define AMD_ZEN_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00) #define AMD_ZEN_BRANCHES_RETIRED RAW_EVENT(0xc2, 0x00) #define AMD_ZEN_BRANCHES_MISPREDICTED RAW_EVENT(0xc3, 0x00) /* * Note! The order and thus the index of the architectural events matters as * support for each event is enumerated via CPUID using the index of the event. */ enum intel_pmu_architectural_events { INTEL_ARCH_CPU_CYCLES_INDEX, INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX, INTEL_ARCH_REFERENCE_CYCLES_INDEX, INTEL_ARCH_LLC_REFERENCES_INDEX, INTEL_ARCH_LLC_MISSES_INDEX, INTEL_ARCH_BRANCHES_RETIRED_INDEX, INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX, INTEL_ARCH_TOPDOWN_SLOTS_INDEX, NR_INTEL_ARCH_EVENTS, }; enum amd_pmu_zen_events { AMD_ZEN_CORE_CYCLES_INDEX, AMD_ZEN_INSTRUCTIONS_INDEX, AMD_ZEN_BRANCHES_INDEX, AMD_ZEN_BRANCH_MISSES_INDEX, NR_AMD_ZEN_EVENTS, }; extern const uint64_t intel_pmu_arch_events[]; extern const uint64_t amd_pmu_zen_events[]; ... const uint64_t intel_pmu_arch_events[] = { INTEL_ARCH_CPU_CYCLES, INTEL_ARCH_INSTRUCTIONS_RETIRED, INTEL_ARCH_REFERENCE_CYCLES, INTEL_ARCH_LLC_REFERENCES, INTEL_ARCH_LLC_MISSES, INTEL_ARCH_BRANCHES_RETIRED, INTEL_ARCH_BRANCHES_MISPREDICTED, INTEL_ARCH_TOPDOWN_SLOTS, }; kvm_static_assert(ARRAY_SIZE(intel_pmu_arch_events) == NR_INTEL_ARCH_EVENTS); const uint64_t amd_pmu_zen_events[] = { AMD_ZEN_CORE_CYCLES, AMD_ZEN_INSTRUCTIONS_RETIRED, AMD_ZEN_BRANCHES_RETIRED, AMD_ZEN_BRANCHES_MISPREDICTED, }; kvm_static_assert(ARRAY_SIZE(amd_pmu_zen_events) == NR_AMD_ZEN_EVENTS);
Sean Christopherson <seanjc@google.com> 于2023年11月7日周二 04:40写道: > > On Mon, Nov 06, 2023, JinrongLiang wrote: > > 在 2023/11/4 21:20, Jim Mattson 写道: > > > > diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/selftests/kvm/include/pmu.h > > > > new file mode 100644 > > > > index 000000000000..987602c62b51 > > > > --- /dev/null > > > > +++ b/tools/testing/selftests/kvm/include/pmu.h > > > > @@ -0,0 +1,84 @@ > > > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > > > +/* > > > > + * Copyright (C) 2023, Tencent, Inc. > > > > + */ > > > > +#ifndef SELFTEST_KVM_PMU_H > > > > +#define SELFTEST_KVM_PMU_H > > > > + > > > > +#include <stdint.h> > > > > + > > > > +#define X86_PMC_IDX_MAX 64 > > > > +#define INTEL_PMC_MAX_GENERIC 32 > > > > > > I think this is actually 15. Note that IA32_PMC0 through IA32_PMC7 > > > have MSR indices from 0xc1 through 0xc8, and MSR 0xcf is > > > IA32_CORE_CAPABILITIES. At the very least, we have to handle > > > non-contiguous MSR indices if we ever go beyond IA32_PMC14. > > There's no reason to define this, it's not used in selftests. > > > > > +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 > > > > + > > > > +#define GP_COUNTER_NR_OFS_BIT 8 > > > > +#define EVENT_LENGTH_OFS_BIT 24 > > > > + > > > > +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) > > > > +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) > > > > +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) > > > > +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) > > These are also unneeded, they're superseded by CPUID properties. > > > > > +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) > > > > +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) > > > > +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) > > > > +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) > > > > +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) > > > > +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) > > > > +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) > > > > +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) > > > > +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) > > > > +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) > > > > +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) > > > > + > > > > +#define PMC_MAX_FIXED 16 > > Also unneeded. > > > > > +#define PMC_IDX_FIXED 32 > > This one is absolutely ridiculous. It's the shift for the enable bit in global > control, which is super obvious from the name. /s > > > > > + > > > > +/* RDPMC offset for Fixed PMCs */ > > > > +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) > > > > +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) > > > > + > > > > +#define FIXED_BITS_MASK 0xFULL > > > > +#define FIXED_BITS_STRIDE 4 > > > > +#define FIXED_0_KERNEL BIT_ULL(0) > > > > +#define FIXED_0_USER BIT_ULL(1) > > > > +#define FIXED_0_ANYTHREAD BIT_ULL(2) > > > > +#define FIXED_0_ENABLE_PMI BIT_ULL(3) > > > > + > > > > +#define fixed_bits_by_idx(_idx, _bits) \ > > > > + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) > > *sigh* And now I see where the "i * 4" stuff in the new test comes from. My > plan is to redo the above as: > > /* RDPMC offset for Fixed PMCs */ > #define FIXED_PMC_RDPMC_METRICS BIT_ULL(29) > #define FIXED_PMC_RDPMC_BASE BIT_ULL(30) > > #define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx))) > > #define FIXED_PMC_KERNEL BIT_ULL(0) > #define FIXED_PMC_USER BIT_ULL(1) > #define FIXED_PMC_ANYTHREAD BIT_ULL(2) > #define FIXED_PMC_ENABLE_PMI BIT_ULL(3) > #define FIXED_PMC_NR_BITS 4 > #define FIXED_PMC_CTRL(_idx, _val) ((_val) << ((_idx) * FIXED_PMC_NR_BITS)) > > > > > +#define AMD64_NR_COUNTERS 4 > > > > +#define AMD64_NR_COUNTERS_CORE 6 > > These too can be dropped for now. > > > > > +#define PMU_CAP_FW_WRITES BIT_ULL(13) > > > > +#define PMU_CAP_LBR_FMT 0x3f > > > > + > > > > +enum intel_pmu_architectural_events { > > > > + /* > > > > + * The order of the architectural events matters as support for each > > > > + * event is enumerated via CPUID using the index of the event. > > > > + */ > > > > + INTEL_ARCH_CPU_CYCLES, > > > > + INTEL_ARCH_INSTRUCTIONS_RETIRED, > > > > + INTEL_ARCH_REFERENCE_CYCLES, > > > > + INTEL_ARCH_LLC_REFERENCES, > > > > + INTEL_ARCH_LLC_MISSES, > > > > + INTEL_ARCH_BRANCHES_RETIRED, > > > > + INTEL_ARCH_BRANCHES_MISPREDICTED, > > > > + NR_INTEL_ARCH_EVENTS, > > > > +}; > > > > + > > > > +enum amd_pmu_k7_events { > > > > + AMD_ZEN_CORE_CYCLES, > > > > + AMD_ZEN_INSTRUCTIONS, > > > > + AMD_ZEN_BRANCHES, > > > > + AMD_ZEN_BRANCH_MISSES, > > > > + NR_AMD_ARCH_EVENTS, > > > > +}; > > > > + > > > > +extern const uint64_t intel_pmu_arch_events[]; > > > > +extern const uint64_t amd_pmu_arch_events[]; > > > > > > AMD doesn't define *any* architectural events. Perhaps > > > amd_pmu_zen_events[], though who knows what Zen5 and beyond will > > > bring? > > > > > > > +extern const int intel_pmu_fixed_pmc_events[]; > > > > + > > > > +#endif /* SELFTEST_KVM_PMU_H */ > > > > diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftests/kvm/lib/pmu.c > > > > new file mode 100644 > > > > index 000000000000..27a6c35f98a1 > > > > --- /dev/null > > > > +++ b/tools/testing/selftests/kvm/lib/pmu.c > > > > @@ -0,0 +1,28 @@ > > > > +// SPDX-License-Identifier: GPL-2.0-only > > > > +/* > > > > + * Copyright (C) 2023, Tencent, Inc. > > > > + */ > > > > + > > > > +#include <stdint.h> > > > > + > > > > +#include "pmu.h" > > > > + > > > > +/* Definitions for Architectural Performance Events */ > > > > +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) > > > > > > There's nothing architectural about this. Perhaps RAW_EVENT() for > > > consistency with perf? > > Works for me. > > > > > +const uint64_t intel_pmu_arch_events[] = { > > > > + [INTEL_ARCH_CPU_CYCLES] = ARCH_EVENT(0x3c, 0x0), > > > > + [INTEL_ARCH_INSTRUCTIONS_RETIRED] = ARCH_EVENT(0xc0, 0x0), > > > > + [INTEL_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0x3c, 0x1), > > > > + [INTEL_ARCH_LLC_REFERENCES] = ARCH_EVENT(0x2e, 0x4f), > > > > + [INTEL_ARCH_LLC_MISSES] = ARCH_EVENT(0x2e, 0x41), > > > > + [INTEL_ARCH_BRANCHES_RETIRED] = ARCH_EVENT(0xc4, 0x0), > > > > + [INTEL_ARCH_BRANCHES_MISPREDICTED] = ARCH_EVENT(0xc5, 0x0), > > > > > > [INTEL_ARCH_TOPDOWN_SLOTS] = ARCH_EVENT(0xa4, 1), > > ... > > > > > @@ -63,7 +50,6 @@ > > > > > > > > #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) > > > > > > Now AMD_ZEN_BRANCHES, above? > > > > Yes, I forgot to replace INTEL_BR_RETIRED, AMD_ZEN_BR_RETIRED and > > INST_RETIRED in pmu_event_filter_test.c and remove their macro definitions. > > Having to go through an array to get a hardcoded value is silly, e.g. it makes > it unnecessarily difficult to reference the encodings because they aren't simple > literals. > > My vote is this: > > #define INTEL_ARCH_CPU_CYCLES RAW_EVENT(0x3c, 0x00) > #define INTEL_ARCH_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00) > #define INTEL_ARCH_REFERENCE_CYCLES RAW_EVENT(0x3c, 0x01) > #define INTEL_ARCH_LLC_REFERENCES RAW_EVENT(0x2e, 0x4f) > #define INTEL_ARCH_LLC_MISSES RAW_EVENT(0x2e, 0x41) > #define INTEL_ARCH_BRANCHES_RETIRED RAW_EVENT(0xc4, 0x00) > #define INTEL_ARCH_BRANCHES_MISPREDICTED RAW_EVENT(0xc5, 0x00) > #define INTEL_ARCH_TOPDOWN_SLOTS RAW_EVENT(0xa4, 0x01) > > #define AMD_ZEN_CORE_CYCLES RAW_EVENT(0x76, 0x00) > #define AMD_ZEN_INSTRUCTIONS_RETIRED RAW_EVENT(0xc0, 0x00) > #define AMD_ZEN_BRANCHES_RETIRED RAW_EVENT(0xc2, 0x00) > #define AMD_ZEN_BRANCHES_MISPREDICTED RAW_EVENT(0xc3, 0x00) > > /* > * Note! The order and thus the index of the architectural events matters as > * support for each event is enumerated via CPUID using the index of the event. > */ > enum intel_pmu_architectural_events { > INTEL_ARCH_CPU_CYCLES_INDEX, > INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX, > INTEL_ARCH_REFERENCE_CYCLES_INDEX, > INTEL_ARCH_LLC_REFERENCES_INDEX, > INTEL_ARCH_LLC_MISSES_INDEX, > INTEL_ARCH_BRANCHES_RETIRED_INDEX, > INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX, > INTEL_ARCH_TOPDOWN_SLOTS_INDEX, > NR_INTEL_ARCH_EVENTS, > }; > > enum amd_pmu_zen_events { > AMD_ZEN_CORE_CYCLES_INDEX, > AMD_ZEN_INSTRUCTIONS_INDEX, > AMD_ZEN_BRANCHES_INDEX, > AMD_ZEN_BRANCH_MISSES_INDEX, > NR_AMD_ZEN_EVENTS, > }; > > extern const uint64_t intel_pmu_arch_events[]; > extern const uint64_t amd_pmu_zen_events[]; > > ... > > > const uint64_t intel_pmu_arch_events[] = { > INTEL_ARCH_CPU_CYCLES, > INTEL_ARCH_INSTRUCTIONS_RETIRED, > INTEL_ARCH_REFERENCE_CYCLES, > INTEL_ARCH_LLC_REFERENCES, > INTEL_ARCH_LLC_MISSES, > INTEL_ARCH_BRANCHES_RETIRED, > INTEL_ARCH_BRANCHES_MISPREDICTED, > INTEL_ARCH_TOPDOWN_SLOTS, > }; > kvm_static_assert(ARRAY_SIZE(intel_pmu_arch_events) == NR_INTEL_ARCH_EVENTS); > > const uint64_t amd_pmu_zen_events[] = { > AMD_ZEN_CORE_CYCLES, > AMD_ZEN_INSTRUCTIONS_RETIRED, > AMD_ZEN_BRANCHES_RETIRED, > AMD_ZEN_BRANCHES_MISPREDICTED, > }; > kvm_static_assert(ARRAY_SIZE(amd_pmu_zen_events) == NR_AMD_ZEN_EVENTS); LGTM, thanks.
diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index a5963ab9215b..44d8d022b023 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -32,6 +32,7 @@ LIBKVM += lib/guest_modes.c LIBKVM += lib/io.c LIBKVM += lib/kvm_util.c LIBKVM += lib/memstress.c +LIBKVM += lib/pmu.c LIBKVM += lib/guest_sprintf.c LIBKVM += lib/rbtree.c LIBKVM += lib/sparsebit.c diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/selftests/kvm/include/pmu.h new file mode 100644 index 000000000000..987602c62b51 --- /dev/null +++ b/tools/testing/selftests/kvm/include/pmu.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023, Tencent, Inc. + */ +#ifndef SELFTEST_KVM_PMU_H +#define SELFTEST_KVM_PMU_H + +#include <stdint.h> + +#define X86_PMC_IDX_MAX 64 +#define INTEL_PMC_MAX_GENERIC 32 +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 + +#define GP_COUNTER_NR_OFS_BIT 8 +#define EVENT_LENGTH_OFS_BIT 24 + +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) + +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) + +#define PMC_MAX_FIXED 16 +#define PMC_IDX_FIXED 32 + +/* RDPMC offset for Fixed PMCs */ +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) + +#define FIXED_BITS_MASK 0xFULL +#define FIXED_BITS_STRIDE 4 +#define FIXED_0_KERNEL BIT_ULL(0) +#define FIXED_0_USER BIT_ULL(1) +#define FIXED_0_ANYTHREAD BIT_ULL(2) +#define FIXED_0_ENABLE_PMI BIT_ULL(3) + +#define fixed_bits_by_idx(_idx, _bits) \ + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) + +#define AMD64_NR_COUNTERS 4 +#define AMD64_NR_COUNTERS_CORE 6 + +#define PMU_CAP_FW_WRITES BIT_ULL(13) +#define PMU_CAP_LBR_FMT 0x3f + +enum intel_pmu_architectural_events { + /* + * The order of the architectural events matters as support for each + * event is enumerated via CPUID using the index of the event. + */ + INTEL_ARCH_CPU_CYCLES, + INTEL_ARCH_INSTRUCTIONS_RETIRED, + INTEL_ARCH_REFERENCE_CYCLES, + INTEL_ARCH_LLC_REFERENCES, + INTEL_ARCH_LLC_MISSES, + INTEL_ARCH_BRANCHES_RETIRED, + INTEL_ARCH_BRANCHES_MISPREDICTED, + NR_INTEL_ARCH_EVENTS, +}; + +enum amd_pmu_k7_events { + AMD_ZEN_CORE_CYCLES, + AMD_ZEN_INSTRUCTIONS, + AMD_ZEN_BRANCHES, + AMD_ZEN_BRANCH_MISSES, + NR_AMD_ARCH_EVENTS, +}; + +extern const uint64_t intel_pmu_arch_events[]; +extern const uint64_t amd_pmu_arch_events[]; +extern const int intel_pmu_fixed_pmc_events[]; + +#endif /* SELFTEST_KVM_PMU_H */ diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftests/kvm/lib/pmu.c new file mode 100644 index 000000000000..27a6c35f98a1 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/pmu.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Tencent, Inc. + */ + +#include <stdint.h> + +#include "pmu.h" + +/* Definitions for Architectural Performance Events */ +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) + +const uint64_t intel_pmu_arch_events[] = { + [INTEL_ARCH_CPU_CYCLES] = ARCH_EVENT(0x3c, 0x0), + [INTEL_ARCH_INSTRUCTIONS_RETIRED] = ARCH_EVENT(0xc0, 0x0), + [INTEL_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0x3c, 0x1), + [INTEL_ARCH_LLC_REFERENCES] = ARCH_EVENT(0x2e, 0x4f), + [INTEL_ARCH_LLC_MISSES] = ARCH_EVENT(0x2e, 0x41), + [INTEL_ARCH_BRANCHES_RETIRED] = ARCH_EVENT(0xc4, 0x0), + [INTEL_ARCH_BRANCHES_MISPREDICTED] = ARCH_EVENT(0xc5, 0x0), +}; + +const uint64_t amd_pmu_arch_events[] = { + [AMD_ZEN_CORE_CYCLES] = ARCH_EVENT(0x76, 0x00), + [AMD_ZEN_INSTRUCTIONS] = ARCH_EVENT(0xc0, 0x00), + [AMD_ZEN_BRANCHES] = ARCH_EVENT(0xc2, 0x00), + [AMD_ZEN_BRANCH_MISSES] = ARCH_EVENT(0xc3, 0x00), +}; diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c index 283cc55597a4..b6e4f57a8651 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c @@ -11,31 +11,18 @@ */ #define _GNU_SOURCE /* for program_invocation_short_name */ -#include "test_util.h" + #include "kvm_util.h" +#include "pmu.h" #include "processor.h" - -/* - * In lieu of copying perf_event.h into tools... - */ -#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) -#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) - -/* End of stuff taken from perf_event.h. */ - -/* Oddly, this isn't in perf_event.h. */ -#define ARCH_PERFMON_BRANCHES_RETIRED 5 +#include "test_util.h" #define NUM_BRANCHES 42 -#define INTEL_PMC_IDX_FIXED 32 - -/* Matches KVM_PMU_EVENT_FILTER_MAX_EVENTS in pmu.c */ -#define MAX_FILTER_EVENTS 300 #define MAX_TEST_EVENTS 10 #define PMU_EVENT_FILTER_INVALID_ACTION (KVM_PMU_EVENT_DENY + 1) #define PMU_EVENT_FILTER_INVALID_FLAGS (KVM_PMU_EVENT_FLAGS_VALID_MASK << 1) -#define PMU_EVENT_FILTER_INVALID_NEVENTS (MAX_FILTER_EVENTS + 1) +#define PMU_EVENT_FILTER_INVALID_NEVENTS (KVM_PMU_EVENT_FILTER_MAX_EVENTS + 1) /* * This is how the event selector and unit mask are stored in an AMD @@ -63,7 +50,6 @@ #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) - /* * "Retired instructions", from Processor Programming Reference * (PPR) for AMD Family 17h Model 01h, Revision B1 Processors, @@ -84,7 +70,7 @@ struct __kvm_pmu_event_filter { __u32 fixed_counter_bitmap; __u32 flags; __u32 pad[4]; - __u64 events[MAX_FILTER_EVENTS]; + __u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; }; /* @@ -729,14 +715,14 @@ static void add_dummy_events(uint64_t *events, int nevents) static void test_masked_events(struct kvm_vcpu *vcpu) { - int nevents = MAX_FILTER_EVENTS - MAX_TEST_EVENTS; - uint64_t events[MAX_FILTER_EVENTS]; + int nevents = KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS; + uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; /* Run the test cases against a sparse PMU event filter. */ run_masked_events_tests(vcpu, events, 0); /* Run the test cases against a dense PMU event filter. */ - add_dummy_events(events, MAX_FILTER_EVENTS); + add_dummy_events(events, KVM_PMU_EVENT_FILTER_MAX_EVENTS); run_masked_events_tests(vcpu, events, nevents); } @@ -818,7 +804,7 @@ static void intel_run_fixed_counter_guest_code(uint8_t fixed_ctr_idx) /* Only OS_EN bit is enabled for fixed counter[idx]. */ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * fixed_ctr_idx)); wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, - BIT_ULL(INTEL_PMC_IDX_FIXED + fixed_ctr_idx)); + BIT_ULL(PMC_IDX_FIXED + fixed_ctr_idx)); __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);