From patchwork Fri Nov 3 10:25:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 161224 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp925182vqu; Fri, 3 Nov 2023 03:26:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGT0wTh+muUIfa2T4azHYFAAd/W+DoBHW9KDcKw8MF+dQW1adUvNpl7CkayXj3NvGTERoMy X-Received: by 2002:a05:6a00:b47:b0:6c0:3e5e:1d46 with SMTP id p7-20020a056a000b4700b006c03e5e1d46mr21515302pfo.21.1699007189936; Fri, 03 Nov 2023 03:26:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1699007189; cv=none; d=google.com; s=arc-20160816; b=ohqU7oJR/Yd+rlqJ5wBMvql0VUGjH3AjDBRDjRF3VdUTxuN5U8CTOrLdbYjCgor5aR vdd9LCZEys1p+G+CoN+g2JqXo4wqAd6Pein8mfWYUSFL4rVyMeM+e40PN0Ts8m8gfobv /1hrg/u7V7KVblwdfg7xVRVG+HtpQ4V0Y/SkUJyvNQB13o/fSDOmTfg1FH/QfXZDK+Vj jYfxzXrMxNWJkoXzqyvkLEa6y5cnfs02fhhsgbnYFUZ9MQ7/3ZpnO0LEYgWqa9XgAi+H 3l+3x1Z9O+95c36ltLOJHJjp2g1+QxiP+F6z/DUXwYthh0eV5HdQhygU3nPowYDAg2NB e7mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2gxCLms1iorr0xnYtUgVyW9H/aj0tiLg6aFzWASagvM=; fh=3eZfXf5jFPKprqHqzv1DRxQ902as4fK5jxtLLEPEL88=; b=PnBhq7B/PrKFAmM+iGc/GHsPSH1qMqT+WMfPSthmXUbG1TBDMR7bDKcTd3qeM6NSaM DOBCvlTb1+DhRUV370jfkhIxmKMsKhLIh1eel8NgT9SeXRihO3Lt0DLPotbOzP0Utff+ hUoPKoPphorJu/BlmUKXViJJI6lw25vswb3a+3RFMeh2KU7/6iXjIk4AbcPajQRx8yS9 J7F05tIDpvKqFJPm8M7AuvkuS3i0VN14y5LBCXLQS/Pg84t56GdZjc4wcXEJ8xQs81JX aLsvNzJO1knX6FgzhUidOv3PW7WL3PT+S+KtOytNR0gUBHeFmu57m7nchJIebTWG8/5d IgDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="k3hE/NbB"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id dw27-20020a056a00369b00b006be0559d029si1357772pfb.109.2023.11.03.03.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 03:26:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="k3hE/NbB"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 210FF83AC0C6; Fri, 3 Nov 2023 03:26:18 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346471AbjKCK0L (ORCPT + 36 others); Fri, 3 Nov 2023 06:26:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230479AbjKCKZ5 (ORCPT ); Fri, 3 Nov 2023 06:25:57 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39F09D4F; Fri, 3 Nov 2023 03:25:42 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1D7B366073E1; Fri, 3 Nov 2023 10:25:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699007141; bh=5p8awgj8e9mrJgUArKBpZscHWI/PcsajbEzfr8YryCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k3hE/NbBI7SY0ZUoVlB6zmyDkR9PCWZPjNLjbiOLAN4mCBj5wSf4O4Ylws0F4mSPG WQMuwg43oQSs0I1gTUolf8XoJLaTZRDnAo/rXWpj6YmAxk3TBABba16IA7M3MA5+uU RqJpfKrRb3mjp8dlOg2ih8IUmclLdB+ChJI5Ux60SCSEFq7WjO3lPHbtpoS5zP95xp hm9H9WLFTC9bX3NYp6zmYAgOdnA1AIGjCuMG66gdhsOagN8QRsb/1JQOAOClwUxWQv TcE5c1fkkx2pn0Q+X5l8xaNMCyVmSciG2meqIXsVpOZhLy71B4Dm1HvIvtsXffCowV oq4leed1/rYtA== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, msp@baylibre.com, amergnat@baylibre.com, yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v3 2/3] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes Date: Fri, 3 Nov 2023 11:25:32 +0100 Message-ID: <20231103102533.69280-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> References: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 03 Nov 2023 03:26:18 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781538162924269862 X-GMAIL-MSGID: 1781538162924269862 The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Reviewed-by: Alexandre Mergnat Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 27 +++++++++++++++------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 5c426a1c94c7..8f713a3341a9 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -415,17 +415,28 @@ static const char * const pwrmcu_parents[] = { "mainpll_d4_d2" }; +/* + * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using + * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate + * in dual output case, which would lead to corruption of functionality loss. + */ static const char * const dp_parents[] = { "clk26m", - "tvdpll1_d2", "tvdpll2_d2", - "tvdpll1_d4", "tvdpll2_d4", - "tvdpll1_d8", "tvdpll2_d8", - "tvdpll1_d16", "tvdpll2_d16" }; +static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 }; + +static const char * const edp_parents[] = { + "clk26m", + "tvdpll1_d2", + "tvdpll1_d4", + "tvdpll1_d8", + "tvdpll1_d16" +}; +static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 }; static const char * const disp_pwm_parents[] = { "clk26m", @@ -957,11 +968,11 @@ static const struct mtk_mux top_mtk_muxes[] = { MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu", pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", - dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp", + dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp", - dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp", + edp_parents, edp_parents_idx, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi", dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",