diff mbox series

x86/resctrl: Fix unused variable warning in cache_alloc_hsw_probe()

Message ID 20231031220534.37730-1-tony.luck@intel.com
State New
Headers
Series x86/resctrl: Fix unused variable warning in cache_alloc_hsw_probe() |

Commit Message

Luck, Tony Oct. 31, 2023, 10:05 p.m. UTC 
  In a "W=1" build gcc throws a warning:

arch/x86/kernel/cpu/resctrl/core.c: In function ‘cache_alloc_hsw_probe’:
arch/x86/kernel/cpu/resctrl/core.c:139:16: warning: variable ‘h’ set but not used

Fix by switching from rdmsr() to rdmsrl() using a single u64 argument
for the MSR value instead of the pair of u32 for the high and low
halves.

Signed-off-by: Tony Luck <tony.luck@intel.com>
---
This has been annoying me for a while as the only warning from the
resctrl code when building with W=1.

N.B. compile tested only. I don't have a Haswell system to check this works.

 arch/x86/kernel/cpu/resctrl/core.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Bagas Sanjaya Nov. 1, 2023, 9:43 a.m. UTC | #1 
On Tue, Oct 31, 2023 at 03:05:34PM -0700, Tony Luck wrote:
> In a "W=1" build gcc throws a warning:
> 
> arch/x86/kernel/cpu/resctrl/core.c: In function ‘cache_alloc_hsw_probe’:
> arch/x86/kernel/cpu/resctrl/core.c:139:16: warning: variable ‘h’ set but not used
> 
> Fix by switching from rdmsr() to rdmsrl() using a single u64 argument
> for the MSR value instead of the pair of u32 for the high and low
> halves.
> 
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
> This has been annoying me for a while as the only warning from the
> resctrl code when building with W=1.
> 
> N.B. compile tested only. I don't have a Haswell system to check this works.
> 
>  arch/x86/kernel/cpu/resctrl/core.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
> index 19e0681f0435..4084131d391d 100644
> --- a/arch/x86/kernel/cpu/resctrl/core.c
> +++ b/arch/x86/kernel/cpu/resctrl/core.c
> @@ -136,15 +136,16 @@ static inline void cache_alloc_hsw_probe(void)
>  {
>  	struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
>  	struct rdt_resource *r  = &hw_res->r_resctrl;
> -	u32 l, h, max_cbm = BIT_MASK(20) - 1;
> +	u32 max_cbm = BIT_MASK(20) - 1;
> +	u64 l3_cbm_0;
>  
>  	if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
>  		return;
>  
> -	rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
> +	rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
>  
>  	/* If all the bits were set in MSR, return success */
> -	if (l != max_cbm)
> +	if (l3_cbm_0 != max_cbm)
>  		return;
>  
>  	hw_res->num_closid = 4;

No noticeable regressions on my Acer Aspire E15 (the laptop uses Intel Core
i3 Haswell), thanks!

Tested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Luck, Tony Nov. 1, 2023, 2:33 p.m. UTC | #2 
> No noticeable regressions on my Acer Aspire E15 (the laptop uses Intel Core
> i3 Haswell), thanks!
>
> Tested-by: Bagas Sanjaya <bagasdotme@gmail.com>

Thanks for reporting that you tested. I don't think a Haswell i3 gets as far as
the piece of code that I changed. the wrmsr_safe() will return non-zero and
the function returns before getting to the piece that I changed.

-Tony
Moger, Babu Nov. 1, 2023, 8:26 p.m. UTC | #3 
Hi Tony,

On 10/31/23 17:05, Tony Luck wrote:
> In a "W=1" build gcc throws a warning:
> 
> arch/x86/kernel/cpu/resctrl/core.c: In function ‘cache_alloc_hsw_probe’:
> arch/x86/kernel/cpu/resctrl/core.c:139:16: warning: variable ‘h’ set but not used
> 
> Fix by switching from rdmsr() to rdmsrl() using a single u64 argument
> for the MSR value instead of the pair of u32 for the high and low
> halves.
> 
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
> This has been annoying me for a while as the only warning from the
> resctrl code when building with W=1.
> 
> N.B. compile tested only. I don't have a Haswell system to check this works.
> 
>  arch/x86/kernel/cpu/resctrl/core.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
> index 19e0681f0435..4084131d391d 100644
> --- a/arch/x86/kernel/cpu/resctrl/core.c
> +++ b/arch/x86/kernel/cpu/resctrl/core.c
> @@ -136,15 +136,16 @@ static inline void cache_alloc_hsw_probe(void)
>  {
>  	struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
>  	struct rdt_resource *r  = &hw_res->r_resctrl;
> -	u32 l, h, max_cbm = BIT_MASK(20) - 1;
> +	u32 max_cbm = BIT_MASK(20) - 1;
> +	u64 l3_cbm_0;
>  
>  	if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
>  		return;
>  
> -	rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
> +	rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);

You are writing 32 bit and reading 64 bit. Why don't you change both to 64
bit?

>  
>  	/* If all the bits were set in MSR, return success */
> -	if (l != max_cbm)
> +	if (l3_cbm_0 != max_cbm)
>  		return;
>  
>  	hw_res->num_closid = 4;
Luck, Tony Nov. 1, 2023, 8:33 p.m. UTC | #4 
> >     if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
> >             return;
> >
> > -   rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
> > +   rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
>
> You are writing 32 bit and reading 64 bit. Why don't you change both to 64
> bit?

wrmsr_safe() writes all 64-bits ... just gets those bits as a pair
of 32-bit arguments for the low and high halves.

I could switch that to wrmsrl_safe() and change max_cbm to be "u64"
to make write & read match. Would that be better?

-Tony
Moger, Babu Nov. 1, 2023, 8:42 p.m. UTC | #5 
On 11/1/23 15:33, Luck, Tony wrote:
>>>     if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
>>>             return;
>>>
>>> -   rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
>>> +   rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
>>
>> You are writing 32 bit and reading 64 bit. Why don't you change both to 64
>> bit?
> 
> wrmsr_safe() writes all 64-bits ... just gets those bits as a pair
> of 32-bit arguments for the low and high halves.
> 
> I could switch that to wrmsrl_safe() and change max_cbm to be "u64"
> to make write & read match. Would that be better?

Yes. That is better.
diff mbox series

Patch

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 19e0681f0435..4084131d391d 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -136,15 +136,16 @@  static inline void cache_alloc_hsw_probe(void)
 {
 	struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
 	struct rdt_resource *r  = &hw_res->r_resctrl;
-	u32 l, h, max_cbm = BIT_MASK(20) - 1;
+	u32 max_cbm = BIT_MASK(20) - 1;
+	u64 l3_cbm_0;
 
 	if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
 		return;
 
-	rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
+	rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
 
 	/* If all the bits were set in MSR, return success */
-	if (l != max_cbm)
+	if (l3_cbm_0 != max_cbm)
 		return;
 
 	hw_res->num_closid = 4;