clk: cdce925: change condition in cdce925_clk_round_rate
Commit Message
To avoid division by zero add check if
divider is zero.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 19fbbbbcd3a3 ("Add TI CDCE925 I2C controlled clock synthesizer driver")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
---
drivers/clk/clk-cdce925.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
@@ -441,7 +441,7 @@ static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long l_parent_rate = *parent_rate;
u16 divider = cdce925_calc_divider(rate, l_parent_rate);
- if (l_parent_rate / divider != rate) {
+ if (divider && l_parent_rate / divider != rate) {
l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
divider = cdce925_calc_divider(rate, l_parent_rate);
*parent_rate = l_parent_rate;