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Mon, 30 Oct 2023 01:38:32 -0500 From: Nikunj A Dadhania To: , , , CC: , , , , , , , , Subject: [PATCH v5 10/14] x86/sev: Change TSC MSR behavior for Secure TSC enabled guests Date: Mon, 30 Oct 2023 12:06:48 +0530 Message-ID: <20231030063652.68675-11-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063652.68675-1-nikunj@amd.com> References: <20231030063652.68675-1-nikunj@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB77:EE_|MN0PR12MB6319:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d676607-123c-4106-8bd3-08dbd912d860 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /tYNyEsoJAMpYa6UD0ZN5sjX2MhZHN9BUtuNqxNT348m3wU5nnmfyPNYwWP6hk0/XFs8uv/lbjqRtyxbInL8mv7aTPyAwUMrlpNVO8ubq8mIXb2cjEGxttI5KPREYfXWwULPAEgG4FKcEOAqg41TYJiJQ3lx7LZMex5c3B1NkJFTJXgaj/mgMmrud26TN5PPWWNjGvY9ezFqKAOtQwE3jLwEJqGKHVIf+E+ocsYCpM9K47wWE64j31zU7uJhVE60m2DmyLrllP6rhJUX+41EOhQCNWMVbMz4oWhw4ey5pxmw2TVo9Od2bLSzGdoRv6v43ZsCIhwO7PaiBidSvFWkEBMPhC0KUk54tvgeK168ktXr1kcXqapTHYp4NFI2ZiDzpC10o3l2xjiutV0LgTyGKme10daZyPyvmjvFYjB6/EXlnuUpXt5+hYsvjkq2LWWzuCwOHSO9CI8xsVpzfk0WiSG25BPgS8MW2FWQw4Ixd458WrQ5NiJ3OyEdFBe8ki9zzDpE3dE690gkLywANInHDrzcnY/g5e0TqjhogMmP1n0R/sBR0gdqk/OaHQQW3p02Ek3ez9W5/3+LLrmEvK1otkFGfzVGYGxiqdk8jvlsNVeGu3QM0ZW+6HZ6JyawKn/HqaX5SbIwKBZ+NuEKKW8AmHRTx/L9O2t8P0yPCJqmDDDvBjimP5ulhqNDuI0uafhzYG2L2q0TlJLJWyUoJPteM9hq7i9DEa6/8qeQDe035o+qwVNDvAs7gObyP40wVLp5iVx2zlC9xMp8I3YQr2qLxA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(136003)(376002)(230922051799003)(1800799009)(186009)(82310400011)(64100799003)(451199024)(40470700004)(46966006)(36840700001)(7696005)(6666004)(478600001)(83380400001)(16526019)(47076005)(26005)(2616005)(1076003)(336012)(426003)(2906002)(5660300002)(7416002)(41300700001)(54906003)(316002)(70206006)(110136005)(4326008)(8676002)(8936002)(70586007)(82740400003)(36860700001)(36756003)(81166007)(356005)(40460700003)(40480700001)(36900700001);DIR:OUT;SFP:1101; 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Sun, 29 Oct 2023 23:39:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161519570550372 X-GMAIL-MSGID: 1781161519570550372 Secure TSC enabled guests should not write MSR_IA32_TSC(10H) register as the subsequent TSC value reads are undefined. MSR_IA32_TSC related accesses should not exit to the hypervisor for such guests. Accesses to MSR_IA32_TSC needs special handling in the #VC handler for the guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored, and reads of MSR_IA32_TSC should return the result of the RDTSC instruction. Signed-off-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky --- arch/x86/kernel/sev.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 9468809d02c7..47e2be38a6bc 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1711,6 +1711,30 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) /* Is it a WRMSR? */ exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; + /* + * TSC related accesses should not exit to the hypervisor when a + * guest is executing with SecureTSC enabled, so special handling + * is required for accesses of MSR_IA32_TSC: + * + * Writes: Writing to MSR_IA32_TSC can cause subsequent reads + * of the TSC to return undefined values, so ignore all + * writes. + * Reads: Reads of MSR_IA32_TSC should return the current TSC + * value, use the value returned by RDTSC. + */ + if (regs->cx == MSR_IA32_TSC && cc_platform_has(CC_ATTR_GUEST_SECURE_TSC)) { + u64 tsc; + + if (exit_info_1) + return ES_OK; + + tsc = rdtsc(); + regs->ax = UINT_MAX & tsc; + regs->dx = UINT_MAX & (tsc >> 32); + + return ES_OK; + } + ghcb_set_rcx(ghcb, regs->cx); if (exit_info_1) { ghcb_set_rax(ghcb, regs->ax);