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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id g5-20020a17090a128500b0027ff8323f07si4609971pja.15.2023.10.29.01.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Oct 2023 01:02:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id BECD080725FE; Sun, 29 Oct 2023 01:01:45 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230080AbjJ2IBJ (ORCPT + 30 others); Sun, 29 Oct 2023 04:01:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbjJ2IBC (ORCPT ); Sun, 29 Oct 2023 04:01:02 -0400 Received: from out30-130.freemail.mail.aliyun.com (out30-130.freemail.mail.aliyun.com [115.124.30.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A772F3; Sun, 29 Oct 2023 01:00:58 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R121e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0Vv31XX4_1698566453; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0Vv31XX4_1698566453) by smtp.aliyun-inc.com; Sun, 29 Oct 2023 16:00:53 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de Subject: [PATCH v1 2/2] dmaengine: idxd: Fix the incorrect descriptions Date: Sun, 29 Oct 2023 16:00:49 +0800 Message-Id: <20231029080049.1482701-3-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231029080049.1482701-1-guanjun@linux.alibaba.com> References: <20231029080049.1482701-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.7 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Sun, 29 Oct 2023 01:01:45 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781076111967175742 X-GMAIL-MSGID: 1781076111967175742 From: Guanjun Fix the incorrect descriptions for the GRPCFG register. No functional changes Signed-off-by: Guanjun Reviewed-by: Dave Jiang --- drivers/dma/idxd/registers.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea1..385a162a55f2 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,15 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to access. + * The GRPCFG register block is divided into three different types, that + * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group + * allows us to move to the register group that's for that particular wq, + * engine or group flag. + * Each register is 64bits. And the ofs in GRPWQCFG gives us the number + * of register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))