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[v2,09/11] riscv: mm: Make asid_bits a local variable

Message ID	20231028231339.3116618-10-samuel.holland@sifive.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Alexandre Ghiti <alexghiti@rivosinc.com>, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Samuel Holland <samuel.holland@sifive.com> Subject: [PATCH v2 09/11] riscv: mm: Make asid_bits a local variable Date: Sat, 28 Oct 2023 16:12:07 -0700 Message-ID: <20231028231339.3116618-10-samuel.holland@sifive.com> In-Reply-To: <20231028231339.3116618-1-samuel.holland@sifive.com> References: <20231028231339.3116618-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: ASID-related and UP-related TLB flush enhancements \| [v2,00/11] riscv: ASID-related and UP-related TLB flush enhancements [v2,01/11] riscv: Improve tlb_flush() [v2,02/11] riscv: Improve flush_tlb_range() for hugetlb pages [v2,03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb [v2,04/11] riscv: Improve flush_tlb_kernel_range() [v2,05/11] riscv: mm: Combine the SMP and UP TLB flush code [v2,06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma [v2,07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros [v2,08/11] riscv: mm: Use a fixed layout for the MM context ID [v2,09/11] riscv: mm: Make asid_bits a local variable [v2,10/11] riscv: mm: Preserve global TLB entries when switching contexts [v2,11/11] riscv: mm: Always use ASID to flush MM contexts

Commit Message

Samuel Holland Oct. 28, 2023, 11:12 p.m. UTC

  This variable is only used inside asids_init().

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

(no changes since v1)

 arch/riscv/mm/context.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

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Patch

diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index b5170ac1b742..43a8bc2d5af4 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -20,7 +20,6 @@ 
 
 DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
 
-static unsigned long asid_bits;
 static unsigned long num_asids;
 
 static atomic_long_t current_version;
@@ -226,7 +225,7 @@  static inline void set_mm(struct mm_struct *prev,
 
 static int __init asids_init(void)
 {
-	unsigned long old;
+	unsigned long asid_bits, old;
 
 	/* Figure-out number of ASID bits in HW */
 	old = csr_read(CSR_SATP);