mbox series

[GIT,PULL] KVM: x86: APIC changes for 6.7

Message ID 20231027204933.3651381-2-seanjc@google.com
State New
Headers
Series [GIT,PULL] KVM: x86: APIC changes for 6.7 |

Pull-request

https://github.com/kvm-x86/linux.git tags/kvm-x86-apic-6.7

Message

Sean Christopherson Oct. 27, 2023, 8:49 p.m. UTC 
  Two small APIC changes for 6.7, both specific to Intel's APICv.

The following changes since commit 5804c19b80bf625c6a9925317f845e497434d6d3:

  Merge tag 'kvm-riscv-fixes-6.6-1' of https://github.com/kvm-riscv/linux into HEAD (2023-09-23 05:35:55 -0400)

are available in the Git repository at:

  https://github.com/kvm-x86/linux.git tags/kvm-x86-apic-6.7

for you to fetch changes up to 629d3698f6958ee6f8131ea324af794f973b12ac:

  KVM: x86: Clear bit12 of ICR after APIC-write VM-exit (2023-09-28 10:42:16 -0700)

----------------------------------------------------------------
KVM x86 APIC changes for 6.7:

 - Purge VMX's posted interrupt descriptor *before* loading APIC state when
   handling KVM_SET_LAPIC.  Purging the PID after loading APIC state results in
   lost APIC timer IRQs as the APIC timer can be armed as part of loading APIC
   state, i.e. can immediately pend an IRQ if the expiry is in the past.

 - Clear the ICR.BUSY bit when handling trap-like x2APIC writes to suppress a
   WARN due to KVM expecting the BUSY bit to be cleared when sending IPIs.

----------------------------------------------------------------
Haitao Shan (1):
      KVM: x86: Fix lapic timer interrupt lost after loading a snapshot.

Tao Su (1):
      KVM: x86: Clear bit12 of ICR after APIC-write VM-exit

 arch/x86/include/asm/kvm-x86-ops.h |  1 +
 arch/x86/include/asm/kvm_host.h    |  1 +
 arch/x86/kvm/lapic.c               | 30 +++++++++++++++++-------------
 arch/x86/kvm/vmx/vmx.c             |  4 ++--
 4 files changed, 21 insertions(+), 15 deletions(-)

Comments

Paolo Bonzini Oct. 31, 2023, 2:15 p.m. UTC | #1 
On Fri, Oct 27, 2023 at 10:49 PM Sean Christopherson <seanjc@google.com> wrote:
>
> Two small APIC changes for 6.7, both specific to Intel's APICv.
>
> The following changes since commit 5804c19b80bf625c6a9925317f845e497434d6d3:
>
>   Merge tag 'kvm-riscv-fixes-6.6-1' of https://github.com/kvm-riscv/linux into HEAD (2023-09-23 05:35:55 -0400)
>
> are available in the Git repository at:
>
>   https://github.com/kvm-x86/linux.git tags/kvm-x86-apic-6.7
>
> for you to fetch changes up to 629d3698f6958ee6f8131ea324af794f973b12ac:
>
>   KVM: x86: Clear bit12 of ICR after APIC-write VM-exit (2023-09-28 10:42:16 -0700)

Pulled, thanks.

Paolo

> ----------------------------------------------------------------
> KVM x86 APIC changes for 6.7:
>
>  - Purge VMX's posted interrupt descriptor *before* loading APIC state when
>    handling KVM_SET_LAPIC.  Purging the PID after loading APIC state results in
>    lost APIC timer IRQs as the APIC timer can be armed as part of loading APIC
>    state, i.e. can immediately pend an IRQ if the expiry is in the past.
>
>  - Clear the ICR.BUSY bit when handling trap-like x2APIC writes to suppress a
>    WARN due to KVM expecting the BUSY bit to be cleared when sending IPIs.
>
> ----------------------------------------------------------------
> Haitao Shan (1):
>       KVM: x86: Fix lapic timer interrupt lost after loading a snapshot.
>
> Tao Su (1):
>       KVM: x86: Clear bit12 of ICR after APIC-write VM-exit
>
>  arch/x86/include/asm/kvm-x86-ops.h |  1 +
>  arch/x86/include/asm/kvm_host.h    |  1 +
>  arch/x86/kvm/lapic.c               | 30 +++++++++++++++++-------------
>  arch/x86/kvm/vmx/vmx.c             |  4 ++--
>  4 files changed, 21 insertions(+), 15 deletions(-)
>