[2/2] x86/barrier: Do not serialize MSR accesses on AMD

  From: "Borislav Petkov (AMD)" <bp@alien8.de>
Date: Fri, 27 Oct 2023 14:24:16 +0200

AMD does not have the requirement for a synchronization barrier when
acccessing a certain group of MSRs. Do not incur that unnecessary
penalty there.

While at it, move to processor.h to avoid include hell. Untangling that
file properly is a matter for another day.

Some notes on the performance aspect of why this is relevant, courtesy
of Kishon VijayAbraham <Kishon.VijayAbraham@amd.com>:

On a AMD Zen4 system with 96 cores, a modified ipi-bench[1] on a VM
shows x2AVIC IPI rate is 3% to 4% lower than AVIC IPI rate. The
ipi-bench is modified so that the IPIs are sent between two vCPUs in the
same CCX. This also requires to pin the vCPU to a physical core to
prevent any latencies. This simulates the use case of pinning vCPUs to
the thread of a single CCX to avoid interrupt IPI latency.

In order to avoid run-to-run variance (for both x2AVIC and AVIC), the
below configurations are done:

  1) Disable Power States in BIOS (to prevent the system from going to
     lower power state)

  2) Run the system at fixed frequency 2500MHz (to prevent the system
     from increasing the frequency when the load is more)

With the above configuration:

*) Performance measured using ipi-bench for AVIC:
  Average Latency:  1124.98ns [Time to send IPI from one vCPU to another vCPU]

  Cumulative throughput: 42.6759M/s [Total number of IPIs sent in a second from
  				     48 vCPUs simultaneously]

*) Performance measured using ipi-bench for x2AVIC:
  Average Latency:  1172.42ns [Time to send IPI from one vCPU to another vCPU]

  Cumulative throughput: 40.9432M/s [Total number of IPIs sent in a second from
  				     48 vCPUs simultaneously]

From above, x2AVIC latency is ~4% more than AVIC. However, the expectation is
x2AVIC performance to be better or equivalent to AVIC. Upon analyzing
the perf captures, it is observed significant time is spent in
weak_wrmsr_fence() invoked by x2apic_send_IPI().

With the fix to skip weak_wrmsr_fence()

*) Performance measured using ipi-bench for x2AVIC:
  Average Latency:  1117.44ns [Time to send IPI from one vCPU to another vCPU]

  Cumulative throughput: 42.9608M/s [Total number of IPIs sent in a second from
  				     48 vCPUs simultaneously]

Comparing the performance of x2AVIC with and without the fix, it can be seen
the performance improves by ~4%.

Performance captured using an unmodified ipi-bench using the 'mesh-ipi' option
with and without weak_wrmsr_fence() on a Zen4 system also showed significant
performance improvement without weak_wrmsr_fence(). The 'mesh-ipi' option ignores
CCX or CCD and just picks random vCPU.

  Average throughput (10 iterations) with weak_wrmsr_fence(),
        Cumulative throughput: 4933374 IPI/s

  Average throughput (10 iterations) without weak_wrmsr_fence(),
        Cumulative throughput: 6355156 IPI/s

[1] https://github.com/bytedance/kvm-utils/tree/master/microbenchmark/ipi-bench

Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
---
 arch/x86/include/asm/barrier.h   | 18 ------------------
 arch/x86/include/asm/processor.h | 18 ++++++++++++++++++
 2 files changed, 18 insertions(+), 18 deletions(-)
  

On Fri, Oct 27, 2023 at 05:34:58PM +0200, Borislav Petkov wrote:

> +static inline void weak_wrmsr_fence(void)
> +{
> +	alternative("mfence; lfence", "", ALT_VENDOR(X86_VENDOR_AMD));
> +}

Well, you see, AFAICT the non-serializing MSRs thing is an Intel thing,
so everything !Intel wants this gone, no?

Definitely the Hygon thing wants this right along with AMD, because
that's basically AMD, no?
  

On Fri, Oct 27, 2023 at 08:56:41PM +0200, Peter Zijlstra wrote:
> Well, you see, AFAICT the non-serializing MSRs thing is an Intel thing,
> so everything !Intel wants this gone, no?
> 
> Definitely the Hygon thing wants this right along with AMD, because
> that's basically AMD, no?

Because of

ce4e240c279a ("x86: add x2apic_wrmsr_fence() to x2apic flush tlb paths")

and it being there since 2009 and getting called unconditionally.

Hygon sure, but the other vendors? I can't even test on some.

Thus the more conservative approach here.
  

On Fri, Oct 27, 2023 at 09:16:33PM +0200, Borislav Petkov wrote:
> Thus the more conservative approach here.

And on a second thought, I don't need any of that new stuff - I simply
need a synthetic flag which says "MSRs need fencing" and set it on
everything but AMD and Hygon. And we've solved this type of issue
gazillion times already - why am I reinventing the wheel?!

:-\
  

On 27/10/2023 8:29 pm, Borislav Petkov wrote:
> On Fri, Oct 27, 2023 at 09:16:33PM +0200, Borislav Petkov wrote:
>> Thus the more conservative approach here.
> And on a second thought, I don't need any of that new stuff - I simply
> need a synthetic flag which says "MSRs need fencing" and set it on
> everything but AMD and Hygon. And we've solved this type of issue
> gazillion times already - why am I reinventing the wheel?!

Quoteth the APM (rev 3.41, June 2023):

16.11.2 WRMSR / RDMSR serialization for x2APIC Register

The WRMSR instruction is used to write the APIC register set in x2APIC
mode. Normally WRMSR is
a serializing instruction, however when accessing x2APIC registers, the
serializing aspect of WRMSR
is relaxed to allow for more efficient access to those registers.
Consequently, a WRMSR write to an
x2APIC register may complete before older store operations are complete
and have become globally
visible. When strong ordering of an x2APIC write access is required with
respect to preceding memory
operations, software can insert a serializing instruction (such as
MFENCE) before the WRMSR
instruction.

So which is right?  This commit message, or the APM?  (and yes, if
you're waiting on an APM update then the commit message should at least
note that one is coming.)


But, to the issue at hand.

There are other non-serialising MSRs on AMD CPUs, including the FS/GS
base MSRs on more modern parts which is enumerated in 8000_0021.eax[1].

So there isn't a boolean "MSRs need fencing, yes/no".  It is vendor
*and* model specific as to whether a particular MSR is serialising or
non-serialising.

*And* it's vendor specific as to what the fencing sequence is.  Intel
require mfence;lfence, while on AMD, mfence suffices.

Most MSR writes don't want to be architecturally serialising, and Intel
are introducing WRMSRNS for this purpose.  But ICR writes *do* need to
be ordered with respect to stores becoming globally visible, and it was
an error for MSR_X2APIC_ICR to be specified as non-serialising.


The only sanity-preserving (pseudo) API for this is something like:

vendor_msr_fence = { mfence;lfence (Intel) | mfence (AMD, Hygon) | ... }

and for each MSR separately, something like:

ALTERNATIVE("", vendor_msr_fence, $VENDOR_NEEDS_MSR_$X_FENCE);

because that's the only one which properly separates "what fence to use"
and "do I need to fence this MSR on the current vendor".

~Andrew
  

On Fri, Oct 27, 2023 at 09:09:05PM +0100, Andrew Cooper wrote:
> There are other non-serialising MSRs on AMD CPUs, including the FS/GS
> base MSRs on more modern parts which is enumerated in 8000_0021.eax[1].
> 
> So there isn't a boolean "MSRs need fencing, yes/no". 

Well, I was implying that "MSRs need fencing" refers to this particular
use case where weak_wrmsr_fence() is used - IA32_TSC_DEADLINE and X2APIC
MSRs.

So the feature bit should be named something more specific:

	X86_FEATURE_APIC_TSC_MSRS_NEED_FENCING

or so.

If we have to do something for the other case, yes, we will have to
either generalize this or add yet another flag.
  

On Fri, Oct 27, 2023 at 09:09:05PM +0100, Andrew Cooper wrote:
> Quoteth the APM (rev 3.41, June 2023):
> 
> 16.11.2 WRMSR / RDMSR serialization for x2APIC Register
> 
> The WRMSR instruction is used to write the APIC register set in x2APIC
> mode. Normally WRMSR is
> a serializing instruction, however when accessing x2APIC registers, the
> serializing aspect of WRMSR
> is relaxed to allow for more efficient access to those registers.
> Consequently, a WRMSR write to an
> x2APIC register may complete before older store operations are complete
> and have become globally
> visible. When strong ordering of an x2APIC write access is required with
> respect to preceding memory
> operations, software can insert a serializing instruction (such as
> MFENCE) before the WRMSR
> instruction.
> 
> So which is right?  This commit message, or the APM?  (and yes, if
> you're waiting on an APM update then the commit message should at least
> note that one is coming.)

To clarify this one: there will be a CPUID bit which states that an
MFENCE is not needed ATM and it'll be added to the APM. I'll add a note
about it to the commit message too.

Thx.