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Thu, 26 Oct 2023 02:41:52 -0500 Received: from xsjarunbala50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 26 Oct 2023 02:41:52 -0500 From: Jay Buddhabhatti To: , , , CC: , , , Jay Buddhabhatti Subject: [PATCH v2 2/2] drivers: clk: zynqmp: update divider round rate logic Date: Thu, 26 Oct 2023 00:41:48 -0700 Message-ID: <20231026074148.7927-3-jay.buddhabhatti@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231026074148.7927-1-jay.buddhabhatti@amd.com> References: <20231026074148.7927-1-jay.buddhabhatti@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|SJ0PR12MB5636:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f345716-9c1e-4a4b-f50c-08dbd5f705bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RZTJtkLIYw64W395kilzcaXyxXN1Kv4+Aft63HZB7i9v2/0A9WAeuBuhTH/QaTUEFEp0KSzPKcc9l6gQnXaBvYC/jY08vpXO6buC1dcHPYB8Z8DBrqcNuwSTBpoMCHDzUWnrPt34aKlvbFNJvcIXq+RfjB5OdzUmQGQPfR8FM/yo6ldf/PJkUz6ALIAhWdR7r4qkbg+4ML17yw95ZxZy4PCXaMTcbxWRSh9tGO3pm/PM8LyoQGdUuaL/j8gBVw1rnsSdNMoWvKTrh7CAaEW6f5MoYSzGQnmxEFxnHDSfYQ6vHTE2Ku/9saYVs8v/BgaaepiOIZqxHJkKPhICLOuKxcOcpxx92VNdHBmei3PY2D4Nv7srJYRE03SAVO5yFIDZMAcE/XWmThYZztYJkja3Ukx0yhZcAu8iTFP6dgZW7QdSqsefd/YM1TZkeUrUVXJckTY0s/yCQORX43nWRhEwPzGXDwLyn+oiG+rvejWZaE41TfIDdiaReKRG1sebtmulQmc1ryYwoYeJtTRhjbqZ7W0uhqy1G+ZotPD/oZ6xx8nv0uGVPC4t05eXzg1nU8XkXoGgMSuwyVsaWVGWVxR6W/HY8r4BBCKj23X9lejxMlASYufTqEmLzZ517DUaUcMC+S58QiDYNHEdJ7rBVXjKuiVXpcbBZ7/O9lLM9y9Dof5xcA5E99Y8Y8yhZmdrbp3e8YcfysdJBruEj4qCzWOuHrbz3Czva85jmZiAkSCyybMhWtDD2s8PRN1p91jZdvaty6h2PkWP5H89r6SQ1mN81w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(376002)(396003)(136003)(230922051799003)(451199024)(186009)(1800799009)(82310400011)(64100799003)(40470700004)(46966006)(36840700001)(40480700001)(40460700003)(83380400001)(4326008)(36860700001)(2906002)(26005)(8676002)(36756003)(82740400003)(47076005)(81166007)(426003)(336012)(44832011)(1076003)(2616005)(356005)(86362001)(8936002)(478600001)(316002)(6666004)(5660300002)(110136005)(41300700001)(70206006)(54906003)(70586007)(36900700001);DIR:OUT;SFP:1101; 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Thu, 26 Oct 2023 00:42:14 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780803054448547878 X-GMAIL-MSGID: 1780803054448547878 Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/divider.c | 66 +++--------------------------------- 1 file changed, 5 insertions(+), 61 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 33a3b2a22659..5a00487ae408 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate, value); } -static void zynqmp_get_divider2_val(struct clk_hw *hw, - unsigned long rate, - struct zynqmp_clk_divider *divider, - u32 *bestdiv) -{ - int div1; - int div2; - long error = LONG_MAX; - unsigned long div1_prate; - struct clk_hw *div1_parent_hw; - struct zynqmp_clk_divider *pdivider; - struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); - - if (!div2_parent_hw) - return; - - pdivider = to_zynqmp_clk_divider(div2_parent_hw); - if (!pdivider) - return; - - div1_parent_hw = clk_hw_get_parent(div2_parent_hw); - if (!div1_parent_hw) - return; - - div1_prate = clk_hw_get_rate(div1_parent_hw); - *bestdiv = 1; - for (div1 = 1; div1 <= pdivider->max_div;) { - for (div2 = 1; div2 <= divider->max_div;) { - long new_error = ((div1_prate / div1) / div2) - rate; - - if (abs(new_error) < abs(error)) { - *bestdiv = div2; - error = new_error; - } - if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) - div2 = div2 << 1; - else - div2++; - } - if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) - div1 = div1 << 1; - else - div1++; - } -} - /** * zynqmp_clk_divider_round_rate() - Round rate of divider clock * @hw: handle between common and hardware-specific interfaces @@ -174,6 +128,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 bestdiv; int ret; + u8 width; /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { @@ -193,23 +148,12 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); - - /* - * In case of two divisors, compute best divider values and return - * divider2 value based on compute value. div1 will be automatically - * set to optimum based on required total divider value. - */ - if (div_type == TYPE_DIV2 && - (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { - zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); - } + width = fls(divider->max_div); - if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) - bestdiv = rate % *prate ? 1 : bestdiv; + rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); - bestdiv = min_t(u32, bestdiv, divider->max_div); - *prate = rate * bestdiv; + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) + *prate = rate; return rate; }