From patchwork Wed Oct 25 20:23:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218689vqb; Wed, 25 Oct 2023 13:27:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEFRVpA8BasJ9Lo4+OHzxtD6eL/nS34v5dR0skp/vo7krX2pA9eF1b6eCsk7XKat/ExQBET X-Received: by 2002:a25:6911:0:b0:da0:39ed:3ebb with SMTP id e17-20020a256911000000b00da039ed3ebbmr6742238ybc.3.1698265631268; Wed, 25 Oct 2023 13:27:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265631; cv=none; d=google.com; s=arc-20160816; b=ZiMOiKiA84aEbruzxzsBRDI1smoxVqghQb1RA8v3XJka9Deccu6A19PiMKtl68eohl N4Ic/QzB9vYGT7nKtFDJJfmYYb+BBNKYbRp8/kWB7XPtqdPMP5MeqpQE5LBmhJqdVukS QkIsTRaV2L7rXqRQrl7qrGJjVZGb49sVnzOplwEGFUY9tb0/QutRxIN3M4LyBL1P8odP pbHmkmlQpvTPmoN8WpBRlIxB33wiNVJdVv6kH4FPYMdZqwjVpkMjGrkMiPxekjQWeceO H9eO4FnyxsdWiP8mDgtdnokf5L7i7GJRTILI/yfTnylMyPn0xn7m8Wz6QlMz/d5jQzIk BEGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TxxAoj3PrwWmIOe2p0tfNOdKkVyofyMHFnQehndBZcc=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=1CHduQBYsno4GocQvxZICKdiP36afJQIrJVDedmLEFvmvkye5NJob4Cr2T1ZdCMj/X EREdLdsuPfWa7ADwUoXYZNv8LxddeTZxhRYjPOCxx2g9CwyCOs8sb8QqHKRAlWbJ4zZ7 SzTT0eDCqQUW+Onl6R5aqxsltwoADrb1Zz+qg1N40AkFvEoxyHmEfy8e8Ihw0PHpXFOu WLCR5jR1A6coaJXzg2/lqRvnX29YVPEhOIPwucNuvEN5Go1i+XymxWWs4RjjUnD6/XJo FeBERpXlS2ga7fpNCUelwoOyTOWzrov7qYNf16jWgVLnU9veiE01SbTQ0vfe+JSWOve9 SKyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=URUZqepl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id e65-20020a251e44000000b00d8d3b231a75si11985288ybe.733.2023.10.25.13.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:27:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=URUZqepl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 0650E80295EC; Wed, 25 Oct 2023 13:27:07 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234920AbjJYU0Z (ORCPT + 25 others); Wed, 25 Oct 2023 16:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234970AbjJYUZv (ORCPT ); Wed, 25 Oct 2023 16:25:51 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FD2ED43 for ; Wed, 25 Oct 2023 13:25:25 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-692c02adeefso117658b3a.3 for ; Wed, 25 Oct 2023 13:25:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265524; x=1698870324; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TxxAoj3PrwWmIOe2p0tfNOdKkVyofyMHFnQehndBZcc=; b=URUZqepln5skTYSBf/XT3SADJoAEDzSaiOx1t4S5Kaj1Z9nHFrKpThnmJKlj3XEX0L IruYc0nrtO3VBVP86UYKHGbmR36Jp+VyUooEVVczi8a73Qa0NN+HCbfDt1A2O+al89Cb MiG+Ne/KCKu/AJYAUteb3WzIASWYmKzO3BKgL1q6CD56xfXQYZwbokP5Y8CHsPzphUma Jx/Gn8EFKQhlz4gYPUnlElEZ9MtN0uNCZt3U8X4QpLAJNKaQyT6blomRDoBfGoOxbQEk mQsfRZN1iN2AUc1eVJ58AfiZHUyGu0K5OshsmcUXAMrl4BnbPl7oNW6+1LU+tqw/47Si EfFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265524; x=1698870324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TxxAoj3PrwWmIOe2p0tfNOdKkVyofyMHFnQehndBZcc=; b=YDd5A6SxVG7ckZtFbjDSCLewyylo2qQZVWtSuUGd05TVl8X1eh6bW1giLZwgv//rpV Mnfk7P1s6/fdc07xEii0pbSTIvZ3mxqK1pgP7sIAxKTazzgru09hRyXjJDdb13SmQB8V 7cIrFjXgfaO6ldk3JFR+l/fLx/UYKdb8MP4/YOcl0FRaMKi/9EyUXVNFDJ2T5lc22ONH myV13akCe1yfOuRcIyCNsyxDFi2JWtS3/9t4U5j+4G4iFuxzsi/xkIdeeyUFILjYNks5 jIBXPl8K4Ubs9i9+kQn3nnSwVB9wgBFXItg7xhVW1dOzptZ/ieVYHHvpI7YGP13WS93x YajQ== X-Gm-Message-State: AOJu0YwVtoCBB/tNgQkDYHKLphvjlehh/aC55A1w+FqNb4uDB7baEpdN BnujD+q6AlPOt5GlOHNQDRRM4Q== X-Received: by 2002:a05:6a00:2d9d:b0:6be:3fbc:763f with SMTP id fb29-20020a056a002d9d00b006be3fbc763fmr15860929pfb.13.1698265524617; Wed, 25 Oct 2023 13:25:24 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:24 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 13/21] irqchip: riscv-intc: Add ACPI support for AIA Date: Thu, 26 Oct 2023 01:53:36 +0530 Message-Id: <20231025202344.581132-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760582951960383 X-GMAIL-MSGID: 1780760582951960383 The RINTC subtype structure in MADT also has information about other interrupt controllers like MMIO. So, save those information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 19 ++++++ drivers/irqchip/irq-riscv-intc.c | 102 ++++++++++++++++++++++++++++++- 2 files changed, 120 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8e10a94430a2..ef102b6fa86e 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,8 +12,27 @@ #include +#ifdef CONFIG_ACPI + +/* + * The ext_intc_id format is as follows: + * Bits [31:24] APLIC/PLIC ID + * Bits [15:0] APLIC IDC ID / PLIC S-Mode Context ID for this hart + */ +#define APLIC_PLIC_ID(x) ((x) >> 24) +#define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) + +int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); +int acpi_get_plic_context(u8 id, u32 idx, int *context_id); +int __init acpi_get_imsic_mmio_info(u32 index, struct resource *res); + +#endif + void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); struct fwnode_handle *riscv_get_intc_hwnode(void); +int acpi_imsic_probe(struct fwnode_handle *parent); #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index bab536bbaf2c..f3aaecde12dd 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -18,6 +18,7 @@ #include #include #include +#include "../pci/pci.h" static struct irq_domain *intc_domain; @@ -195,13 +196,100 @@ IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI +struct rintc_data { + u32 ext_intc_id; + unsigned long hart_id; + u64 imsic_addr; + u32 imsic_size; +}; + +static u32 nr_rintc; +static struct rintc_data *rintc_acpi_data[NR_CPUS]; + +int acpi_get_intc_index_hartid(u32 index, unsigned long *hartid) +{ + if (index >= nr_rintc) + return -1; + + *hartid = rintc_acpi_data[index]->hart_id; + return 0; +} + +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid) +{ + int i, j = 0; + + for (i = 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) == id) { + if (idx == j) { + *hartid = rintc_acpi_data[i]->hart_id; + return 0; + } + j++; + } + } + + return -1; +} + +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts) +{ + int i, j = 0; + + for (i = 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) == id) + j++; + } + + *nr_contexts = j; +} + +int acpi_get_plic_context(u8 id, u32 idx, int *context_id) +{ + int i, j = 0; + + for (i = 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) == id) { + if (idx == j) { + *context_id = IDC_CONTEXT_ID(rintc_acpi_data[i]->ext_intc_id); + return 0; + } + + j++; + } + } + + return -1; +} + +int acpi_get_imsic_mmio_info(u32 index, struct resource *res) +{ + if (index >= nr_rintc) + return -1; + + res->start = rintc_acpi_data[index]->imsic_addr; + res->end = res->start + rintc_acpi_data[index]->imsic_size - 1; + res->flags = IORESOURCE_MEM; + return 0; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { struct fwnode_handle *fn; struct acpi_madt_rintc *rintc; + int rc; rintc = (struct acpi_madt_rintc *)header; + rintc_acpi_data[nr_rintc] = kzalloc(sizeof(*rintc_acpi_data[0]), GFP_KERNEL); + if (!rintc_acpi_data[nr_rintc]) + return -ENOMEM; + + rintc_acpi_data[nr_rintc]->ext_intc_id = rintc->ext_intc_id; + rintc_acpi_data[nr_rintc]->hart_id = rintc->hart_id; + rintc_acpi_data[nr_rintc]->imsic_addr = rintc->imsic_addr; + rintc_acpi_data[nr_rintc]->imsic_size = rintc->imsic_size; + nr_rintc++; /* * The ACPI MADT will have one INTC for each CPU (or HART) @@ -218,7 +306,19 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, return -ENOMEM; } - return riscv_intc_init_common(fn); + rc = riscv_intc_init_common(fn); + if (rc) { + irq_domain_free_fwnode(fn); + return rc; + } + + /* + * MSI controller (IMSIC) in RISC-V is optional. So, unless + * IMSIC is discovered, set system wide MSI support as + * unsupported. Once IMSIC is probed, MSI support will be set. + */ + pci_no_msi(); + return 0; } IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,