[v11,06/14] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller
Commit Message
We add DT bindings document for the RISC-V incoming MSI controller
(IMSIC) defined by the RISC-V advanced interrupt architecture (AIA)
specification.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++
1 file changed, 172 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
Comments
On Mon, Oct 23, 2023 at 10:57:52PM +0530, Anup Patel wrote:
> We add DT bindings document for the RISC-V incoming MSI controller
> (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA)
> specification.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++
> 1 file changed, 172 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
> new file mode 100644
> index 000000000000..84976f17a4a1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
> @@ -0,0 +1,172 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Incoming MSI Controller (IMSIC)
> +
> +maintainers:
> + - Anup Patel <anup@brainfault.org>
> +
> +description: |
> + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
> + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
> + AIA specification can be found at https://github.com/riscv/riscv-aia.
> +
> + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
> + for each privilege level (machine or supervisor). The configuration of
> + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
an IMSIC
> + space to receive MSIs from devices. Each IMSIC interrupt file supports a
> + fixed number of interrupt identities (to distinguish MSIs from devices)
> + which is same for given privilege level across CPUs (or HARTs).
which is the same for a given
> +
> + The device tree of a RISC-V platform will have one IMSIC device tree node
> + for each privilege level (machine or supervisor) which collectively describe
> + IMSIC interrupt files at that privilege level across CPUs (or HARTs).
s/at that privilege level/for their respective privilege levels/
> +
> + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
> + follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
An IMSIC
> + group is a set of IMSIC interrupt files co-located in MMIO space and we can
> + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
> + RISC-V platform. The MSI target address of a IMSIC interrupt file at given
an IMSIC interrupt file at a given
> + privilege level (machine or supervisor) encodes group index, HART index,
> + and guest index (shown below).
> +
> + XLEN-1 > (HART Index MSB) 12 0
> + | | | |
> + -------------------------------------------------------------
> + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
> + -------------------------------------------------------------
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> + - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - qemu,imsics
> + - const: riscv,imsics
> +
> + reg:
> + minItems: 1
> + maxItems: 16384
> + description:
> + Base address of each IMSIC group.
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 0
> +
> + msi-controller: true
> +
> + "#msi-cells":
> + const: 0
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 16384
> + description:
> + This property represents the set of CPUs (or HARTs) for which given
which a given
> + device tree node describes the IMSIC interrupt files. Each node pointed
> + to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
> + HART) as parent.
as its parent
> +
> + riscv,num-ids:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 63
> + maximum: 2047
> + description:
> + Number of interrupt identities supported by IMSIC interrupt file.
by an IMSIC interrupt file
> +
> + riscv,num-guest-ids:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 63
> + maximum: 2047
> + description:
> + Number of interrupt identities are supported by IMSIC guest interrupt
which are supported by an IMSIC guest interrupt file
> + file. When not specified it is assumed to be same as specified by the
the same
> + riscv,num-ids property.
> +
> + riscv,guest-index-bits:
> + minimum: 0
> + maximum: 7
> + default: 0
> + description:
> + Number of guest index bits in the MSI target address.
> +
> + riscv,hart-index-bits:
> + minimum: 0
> + maximum: 15
> + description:
> + Number of HART index bits in the MSI target address. When not
> + specified it is calculated based on the interrupts-extended property.
> +
> + riscv,group-index-bits:
> + minimum: 0
> + maximum: 7
> + default: 0
> + description:
> + Number of group index bits in the MSI target address.
> +
> + riscv,group-index-shift:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 55
> + default: 24
> + description:
> + The least significant bit position of the group index bits in the
> + MSI target address.
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-controller
> + - msi-controller
> + - "#msi-cells"
> + - interrupts-extended
> + - riscv,num-ids
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + // Example 1 (Machine-level IMSIC files with just one group):
> +
> + interrupt-controller@24000000 {
> + compatible = "qemu,imsics", "riscv,imsics";
> + interrupts-extended = <&cpu1_intc 11>,
> + <&cpu2_intc 11>,
> + <&cpu3_intc 11>,
> + <&cpu4_intc 11>;
> + reg = <0x28000000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + msi-controller;
> + #msi-cells = <0>;
> + riscv,num-ids = <127>;
> + };
> +
> + - |
> + // Example 2 (Supervisor-level IMSIC files with two groups):
> +
> + interrupt-controller@28000000 {
> + compatible = "qemu,imsics", "riscv,imsics";
> + interrupts-extended = <&cpu1_intc 9>,
> + <&cpu2_intc 9>,
> + <&cpu3_intc 9>,
> + <&cpu4_intc 9>;
> + reg = <0x28000000 0x2000>, /* Group0 IMSICs */
> + <0x29000000 0x2000>; /* Group1 IMSICs */
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + msi-controller;
> + #msi-cells = <0>;
> + riscv,num-ids = <127>;
> + riscv,group-index-bits = <1>;
> + riscv,group-index-shift = <24>;
> + };
> +...
> --
> 2.34.1
>
Thanks,
drew
new file mode 100644
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Incoming MSI Controller (IMSIC)
+
+maintainers:
+ - Anup Patel <anup@brainfault.org>
+
+description: |
+ The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
+ MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
+ AIA specification can be found at https://github.com/riscv/riscv-aia.
+
+ The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
+ for each privilege level (machine or supervisor). The configuration of
+ a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
+ space to receive MSIs from devices. Each IMSIC interrupt file supports a
+ fixed number of interrupt identities (to distinguish MSIs from devices)
+ which is same for given privilege level across CPUs (or HARTs).
+
+ The device tree of a RISC-V platform will have one IMSIC device tree node
+ for each privilege level (machine or supervisor) which collectively describe
+ IMSIC interrupt files at that privilege level across CPUs (or HARTs).
+
+ The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
+ follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
+ group is a set of IMSIC interrupt files co-located in MMIO space and we can
+ have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
+ RISC-V platform. The MSI target address of a IMSIC interrupt file at given
+ privilege level (machine or supervisor) encodes group index, HART index,
+ and guest index (shown below).
+
+ XLEN-1 > (HART Index MSB) 12 0
+ | | | |
+ -------------------------------------------------------------
+ |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
+ -------------------------------------------------------------
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+ - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qemu,imsics
+ - const: riscv,imsics
+
+ reg:
+ minItems: 1
+ maxItems: 16384
+ description:
+ Base address of each IMSIC group.
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 0
+
+ msi-controller: true
+
+ "#msi-cells":
+ const: 0
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 16384
+ description:
+ This property represents the set of CPUs (or HARTs) for which given
+ device tree node describes the IMSIC interrupt files. Each node pointed
+ to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
+ HART) as parent.
+
+ riscv,num-ids:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 63
+ maximum: 2047
+ description:
+ Number of interrupt identities supported by IMSIC interrupt file.
+
+ riscv,num-guest-ids:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 63
+ maximum: 2047
+ description:
+ Number of interrupt identities are supported by IMSIC guest interrupt
+ file. When not specified it is assumed to be same as specified by the
+ riscv,num-ids property.
+
+ riscv,guest-index-bits:
+ minimum: 0
+ maximum: 7
+ default: 0
+ description:
+ Number of guest index bits in the MSI target address.
+
+ riscv,hart-index-bits:
+ minimum: 0
+ maximum: 15
+ description:
+ Number of HART index bits in the MSI target address. When not
+ specified it is calculated based on the interrupts-extended property.
+
+ riscv,group-index-bits:
+ minimum: 0
+ maximum: 7
+ default: 0
+ description:
+ Number of group index bits in the MSI target address.
+
+ riscv,group-index-shift:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 55
+ default: 24
+ description:
+ The least significant bit position of the group index bits in the
+ MSI target address.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - msi-controller
+ - "#msi-cells"
+ - interrupts-extended
+ - riscv,num-ids
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ // Example 1 (Machine-level IMSIC files with just one group):
+
+ interrupt-controller@24000000 {
+ compatible = "qemu,imsics", "riscv,imsics";
+ interrupts-extended = <&cpu1_intc 11>,
+ <&cpu2_intc 11>,
+ <&cpu3_intc 11>,
+ <&cpu4_intc 11>;
+ reg = <0x28000000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ msi-controller;
+ #msi-cells = <0>;
+ riscv,num-ids = <127>;
+ };
+
+ - |
+ // Example 2 (Supervisor-level IMSIC files with two groups):
+
+ interrupt-controller@28000000 {
+ compatible = "qemu,imsics", "riscv,imsics";
+ interrupts-extended = <&cpu1_intc 9>,
+ <&cpu2_intc 9>,
+ <&cpu3_intc 9>,
+ <&cpu4_intc 9>;
+ reg = <0x28000000 0x2000>, /* Group0 IMSICs */
+ <0x29000000 0x2000>; /* Group1 IMSICs */
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ msi-controller;
+ #msi-cells = <0>;
+ riscv,num-ids = <127>;
+ riscv,group-index-bits = <1>;
+ riscv,group-index-shift = <24>;
+ };
+...