diff mbox series

[3/7] irqchip/renesas-rzg2l: add macros to retrieve TITSR index and associated selector

Message ID 20231023102223.1309614-4-claudiu.beznea.uj@bp.renesas.com
State New
Headers
Series irqchip/renesas-rzg2l: add support for RZ/G3S SoC |

Commit Message

claudiu beznea Oct. 23, 2023, 10:22 a.m. UTC 
  From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add macros to retrieve TITSR register index and associated selector.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzg2l.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

Comments

Thomas Gleixner Oct. 27, 2023, 5:58 p.m. UTC | #1 
On Mon, Oct 23 2023 at 13:22, Claudiu wrote:

> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add macros to retrieve TITSR register index and associated selector.

This is not what the patch actually does. Also please explain the WHY
and not the WHAT.
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index fe8d516f3614..9ce0d6d67486 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -28,8 +28,7 @@ 
 #define ISCR				0x10
 #define IITSR				0x14
 #define TSCR				0x20
-#define TITSR0				0x24
-#define TITSR1				0x28
+#define TITSR(n)			(0x24 + (n) * 4)
 #define TITSR0_MAX_INT			16
 #define TITSEL_WIDTH			0x2
 #define TSSR(n)				(0x30 + ((n) * 4))
@@ -45,6 +44,8 @@ 
 #define TITSR_TITSEL_EDGE_FALLING	1
 #define TITSR_TITSEL_LEVEL_HIGH		2
 #define TITSR_TITSEL_LEVEL_LOW		3
+#define TITSR_HWIRQ_TO_INDEX(hwirq)	((hwirq) >> TITSR0_MAX_INT)
+#define TITSR_HWIRQ_TO_SEL(hwirq)	((hwirq) & 0xF)		/* 0xF = TITSR0_MAX_INT - 1*/
 
 #define IITSR_IITSEL(n, sense)		((sense) << ((n) * 2))
 #define IITSR_IITSEL_LEVEL_LOW		0
@@ -185,12 +186,10 @@  static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
 
 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
 {
+	unsigned int hwirq = irqd_to_hwirq(d) - IRQC_TINT_START;
 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
-	unsigned int hwirq = irqd_to_hwirq(d);
-	u32 titseln = hwirq - IRQC_TINT_START;
-	u32 offset;
+	u32 index, sel, reg;
 	u8 sense;
-	u32 reg;
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_EDGE_RISING:
@@ -205,17 +204,14 @@  static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
 		return -EINVAL;
 	}
 
-	offset = TITSR0;
-	if (titseln >= TITSR0_MAX_INT) {
-		titseln -= TITSR0_MAX_INT;
-		offset = TITSR1;
-	}
+	index = TITSR_HWIRQ_TO_INDEX(hwirq);
+	sel = TITSR_HWIRQ_TO_SEL(hwirq);
 
 	raw_spin_lock(&priv->lock);
-	reg = readl_relaxed(priv->base + offset);
-	reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
-	reg |= sense << (titseln * TITSEL_WIDTH);
-	writel_relaxed(reg, priv->base + offset);
+	reg = readl_relaxed(priv->base + TITSR(index));
+	reg &= ~(IRQ_MASK << (sel * TITSEL_WIDTH));
+	reg |= sense << (sel * TITSEL_WIDTH);
+	writel_relaxed(reg, priv->base + TITSR(index));
 	raw_spin_unlock(&priv->lock);
 
 	return 0;