diff mbox series

[RFC,08/12] riscv: Enable NMIs during irqs disabled context

Message ID	20231023082911.23242-9-luxu.kernel@bytedance.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; From: Xu Lu <luxu.kernel@bytedance.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu <luxu.kernel@bytedance.com> Subject: [RFC 08/12] riscv: Enable NMIs during irqs disabled context Date: Mon, 23 Oct 2023 16:29:07 +0800 Message-Id: <20231023082911.23242-9-luxu.kernel@bytedance.com> In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: Introduce Pseudo NMI \| [RFC,00/12] riscv: Introduce Pseudo NMI [RFC,01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI [RFC,02/12] riscv: Make CSR_IE register part of context [RFC,03/12] riscv: Switch to CSR_IE masking when disabling irqs [RFC,04/12] riscv: Switch back to CSR_STATUS masking when going idle [RFC,05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest [RFC,06/12] riscv: Allow requesting irq as pseudo NMI [RFC,07/12] riscv: Handle pseudo NMI in arch irq handler [RFC,08/12] riscv: Enable NMIs during irqs disabled context [RFC,09/12] riscv: Enable NMIs during exceptions [RFC,10/12] riscv: Enable NMIs during interrupt handling [RFC,11/12] riscv: Request pmu overflow interrupt as NMI [RFC,12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default

Commit Message

Xu Lu Oct. 23, 2023, 8:29 a.m. UTC

  This commit allows NMIs to happen even when irqs are disabled. When
disabling irqs, we mask all normal irqs via clearing corresponding bits
in CSR_IE while leaving NMI bits alone.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
 arch/riscv/include/asm/irqflags.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
index 9700a17a003a..42f7803582df 100644
--- a/arch/riscv/include/asm/irqflags.h
+++ b/arch/riscv/include/asm/irqflags.h
@@ -54,13 +54,13 @@  static inline void arch_local_irq_enable(void)
 /* unconditionally disable interrupts */
 static inline void arch_local_irq_disable(void)
 {
-	csr_clear(CSR_IE, irqs_enabled_ie);
+	csr_clear(CSR_IE, ~ALLOWED_NMI_MASK);
 }
 
 /* get status and disable interrupts */
 static inline unsigned long arch_local_irq_save(void)
 {
-	return csr_read_clear(CSR_IE, irqs_enabled_ie);
+	return csr_read_clear(CSR_IE, ~ALLOWED_NMI_MASK);
 }
 
 /* test flags */