diff mbox series

[RFC,07/12] riscv: Handle pseudo NMI in arch irq handler

Message ID	20231023082911.23242-8-luxu.kernel@bytedance.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; From: Xu Lu <luxu.kernel@bytedance.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu <luxu.kernel@bytedance.com> Subject: [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Date: Mon, 23 Oct 2023 16:29:06 +0800 Message-Id: <20231023082911.23242-8-luxu.kernel@bytedance.com> In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: Introduce Pseudo NMI \| [RFC,00/12] riscv: Introduce Pseudo NMI [RFC,01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI [RFC,02/12] riscv: Make CSR_IE register part of context [RFC,03/12] riscv: Switch to CSR_IE masking when disabling irqs [RFC,04/12] riscv: Switch back to CSR_STATUS masking when going idle [RFC,05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest [RFC,06/12] riscv: Allow requesting irq as pseudo NMI [RFC,07/12] riscv: Handle pseudo NMI in arch irq handler [RFC,08/12] riscv: Enable NMIs during irqs disabled context [RFC,09/12] riscv: Enable NMIs during exceptions [RFC,10/12] riscv: Enable NMIs during interrupt handling [RFC,11/12] riscv: Request pmu overflow interrupt as NMI [RFC,12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default

Commit Message

Xu Lu Oct. 23, 2023, 8:29 a.m. UTC

  This commit handles pseudo NMI in arch irq handler. We enter NMI context
before handling NMI and keeps all interrupts disabled during NMI handling
to avoid interrupt nesting.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Signed-off-by: Hangjing Li <lihangjing@bytedance.com>
---
 drivers/irqchip/irq-riscv-intc.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff mbox series

Patch

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 83a0a744fce6..c672c0c64d5d 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -20,6 +20,26 @@ 
 
 static struct irq_domain *intc_domain;
 
+#ifdef CONFIG_RISCV_PSEUDO_NMI
+
+static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
+{
+	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
+
+	if (unlikely(cause >= BITS_PER_LONG))
+		panic("unexpected interrupt cause");
+
+	if (is_nmi(cause)) {
+		nmi_enter();
+		generic_handle_domain_nmi(intc_domain, cause);
+		nmi_exit();
+	} else {
+		generic_handle_domain_irq(intc_domain, cause);
+	}
+}
+
+#else /* CONFIG_RISCV_PSEUDO_NMI */
+
 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
@@ -30,6 +50,8 @@  static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 	generic_handle_domain_irq(intc_domain, cause);
 }
 
+#endif /* CONFIG_RISCV_PSEUDO_NMI */
+
 /*
  * On RISC-V systems local interrupts are masked or unmasked by writing
  * the SIE (Supervisor Interrupt Enable) CSR.  As CSRs can only be written