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Mon, 23 Oct 2023 01:30:23 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Date: Mon, 23 Oct 2023 16:29:10 +0800 Message-Id: <20231023082911.23242-12-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:31:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534367784151268 X-GMAIL-MSGID: 1780534367784151268 This commit registers pmu overflow interrupt as NMI to improve the accuracy of perf sampling. Signed-off-by: Xu Lu --- arch/riscv/include/asm/irqflags.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 23 +++++++++++++++++++---- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 6a709e9c69ca..be840e297559 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -12,7 +12,7 @@ #ifdef CONFIG_RISCV_PSEUDO_NMI -#define __ALLOWED_NMI_MASK 0 +#define __ALLOWED_NMI_MASK BIT(IRQ_PMU_OVF) #define ALLOWED_NMI_MASK (__ALLOWED_NMI_MASK & irqs_enabled_ie) static inline bool nmi_allowed(int irq) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 995b501ec721..85abb7dd43b9 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -760,6 +760,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) { + int ret = 0; struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); @@ -778,20 +779,30 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); -#ifndef CONFIG_RISCV_PSEUDO_NMI +#ifdef CONFIG_RISCV_PSEUDO_NMI + ret = prepare_percpu_nmi(riscv_pmu_irq); + if (ret != 0) { + pr_err("Failed to prepare percpu nmi:%d\n", ret); + return ret; + } + enable_percpu_nmi(riscv_pmu_irq, IRQ_TYPE_NONE); +#else csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); -#endif enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); +#endif } - return 0; + return ret; } static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { +#ifdef CONFIG_RISCV_PSEUDO_NMI + disable_percpu_nmi(riscv_pmu_irq); + teardown_percpu_nmi(riscv_pmu_irq); +#else disable_percpu_irq(riscv_pmu_irq); -#ifndef CONFIG_RISCV_PSEUDO_NMI csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); #endif } @@ -835,7 +846,11 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde return -ENODEV; } +#ifdef CONFIG_RISCV_PSEUDO_NMI + ret = request_percpu_nmi(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); +#else ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); +#endif if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); return ret;