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Mon, 23 Oct 2023 11:06:50 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 11:06:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 11:06:47 +0800 From: Yunfei Dong To: Sebastian Fricke , =?utf-8?q?N=C3=ADcola?= =?utf-8?q?s_F_=2E_R_=2E_A_=2E_Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , "Steve Cho" , Yunfei Dong , , , , , , Subject: [PATCH v2,6/7] media: mediatek: vcodec: Set the supported vp9 level for each platform Date: Mon, 23 Oct 2023 11:06:39 +0800 Message-ID: <20231023030640.16393-7-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231023030640.16393-1-yunfei.dong@mediatek.com> References: <20231023030640.16393-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.983200-8.000000 X-TMASE-MatchedRID: iCbNFKe75FjnWmH8Qoh70pyBsp6+TmyGjiWciALpTNMx3z93vsEFGtvM SB0gigG5ThbvLLI8RvNELJsmoli+adAjTMr/wDJyFp8tduyF+iC2McZY43zJ423D6f6IpbLI2ug QZCK503JPN9Ds5e3i44Ay6p60ZV62fJ5/bZ6npdiujVRFkkVsmyMHa3Cnrmnvr9Qtj+WbdnoExP 333s+6T59oJbLvgyEgl5rvPYMic2rKKOiar1G+1/VY2XWHPqpnLxQDRLNsvk2n4W5Hf9z78m1Rj oup2VCcWve+eVz4Pp5Vk5utmQ1VlGVF3+d9rnoxXsgQSqx49gY= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.983200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: D7E391B8B2E2864A25DD15FB509BE6CF248AB038746AD37B7F694E7069E1CDDD2000:8 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sun, 22 Oct 2023 20:07:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780514050912783758 X-GMAIL-MSGID: 1780514050912783758 Set the maximum VP9 codec level for each platform. The various mediatek platforms support different levels for decoding, the level of the codec limits among others the maximum resolution, bit rate, frame rate and compression rate for the decoder. Signed-off-by: Yunfei Dong Reviewed-by: Sebastian Fricke Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index 816709fe0f18..eb8590edb579 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -113,6 +113,15 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { }, .codec_type = V4L2_PIX_FMT_VP9_FRAME, }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_VP9_LEVEL, + .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + .def = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + }, + .codec_type = V4L2_PIX_FMT_VP9_FRAME, + }, { .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, @@ -603,6 +612,26 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, }; } +static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8192: + case MTK_VDEC_MT8188: + cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; + break; + case MTK_VDEC_MT8195: + cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; + break; + case MTK_VDEC_MT8186: + cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; + break; + default: + cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0; + break; + }; +} + static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { @@ -615,6 +644,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, mtk_vcodec_dec_fill_h265_level(cfg, ctx); mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def); break; + case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: + mtk_vcodec_dec_fill_vp9_level(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported level: %lld %lld", cfg->max, cfg->def); + break; case V4L2_CID_MPEG_VIDEO_H264_PROFILE: mtk_vcodec_dec_fill_h264_profile(cfg, ctx); mtk_v4l2_vdec_dbg(3, ctx, "h264 supported profile: %lld %lld", cfg->max,