diff mbox series

[V2] arm64: dts: imx8mp: Add NPU Node

Message ID 20231022161911.10792-1-aford173@gmail.com
State New
Headers
Series [V2] arm64: dts: imx8mp: Add NPU Node |

Commit Message

Adam Ford Oct. 22, 2023, 4:19 p.m. UTC 
  The NPU is based on the Vivante GC8000 and its power-domain
is controlled my pgc_mlmix.  Since the power-domain uses
some of these clocks, setup the clock parent and rates
inside the power-domain, and add the NPU node.

The data sheet states the CLK_ML_AHB should be 300MHz for
nominal, but 800MHz clock will divide down to 266 instead.
Boards which operate in over-drive mode should update the
clocks on their boards accordingly.  When the driver loads,
the NPU numerates as:

 etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002

Signed-off-by: Adam Ford <aford173@gmail.com>
---

V2:  Move the clock parent and rate assignments to the ppc_mlmix node
     since clock parents should be configured before they are used,
     and pgc_mlmix uses them first.
     Slow the clock rates down to confirm to nominal mode instead of
     overdrive mode.

Comments

Alexander Stein Oct. 23, 2023, 1:23 p.m. UTC | #1 
Hi Adam,

thanks for the update.

Am Sonntag, 22. Oktober 2023, 18:19:10 CEST schrieb Adam Ford:
> The NPU is based on the Vivante GC8000 and its power-domain
> is controlled my pgc_mlmix.  Since the power-domain uses
> some of these clocks, setup the clock parent and rates
> inside the power-domain, and add the NPU node.
> 
> The data sheet states the CLK_ML_AHB should be 300MHz for
> nominal, but 800MHz clock will divide down to 266 instead.
> Boards which operate in over-drive mode should update the
> clocks on their boards accordingly.  When the driver loads,
> the NPU numerates as:
> 
>  etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002

There seems to be some race condition upon GPU/NPU detection. Sometimes I get 
these messages:
[    1.338100] etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
[    1.344469] etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
[    1.350748] etnaviv-gpu 38500000.npu: model: GC0, revision: 0
[    1.356514] etnaviv-gpu 38500000.npu: Unknown GPU model

Sometimes I see GC8000 being detected as you have written. Despite that the 
patch itself looks good.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
> 
> V2:  Move the clock parent and rate assignments to the ppc_mlmix node
>      since clock parents should be configured before they are used,
>      and pgc_mlmix uses them first.
>      Slow the clock rates down to confirm to nominal mode instead of
>      overdrive mode.
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> c9a610ba4836..a18b9ba98ea2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -887,6 +887,15 @@ pgc_mlmix: power-domain@24 {
>  						clocks = <&clk 
IMX8MP_CLK_ML_AXI>,
>  							 <&clk 
IMX8MP_CLK_ML_AHB>,
>  							 <&clk 
IMX8MP_CLK_NPU_ROOT>;
> +						assigned-clocks = 
<&clk IMX8MP_CLK_ML_CORE>,
> +								
  <&clk IMX8MP_CLK_ML_AXI>,
> +								
  <&clk IMX8MP_CLK_ML_AHB>;
> +						assigned-clock-
parents = <&clk IMX8MP_SYS_PLL1_800M>,
> +								
	 <&clk IMX8MP_SYS_PLL1_800M>,
> +								
	 <&clk IMX8MP_SYS_PLL1_800M>;
> +						assigned-clock-
rates = <800000000>,
> +								
       <800000000>,
> +								
       <300000000>;
>  					};
>  				};
>  			};
> @@ -2012,6 +2021,18 @@ vpumix_blk_ctrl: blk-ctrl@38330000 {
>  			interconnect-names = "g1", "g2", "vc8000e";
>  		};
> 
> +		npu: npu@38500000 {
> +			compatible = "vivante,gc";
> +			reg = <0x38500000 0x200000>;
> +			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
> +				 <&clk IMX8MP_CLK_NPU_ROOT>,
> +				 <&clk IMX8MP_CLK_ML_AXI>,
> +				 <&clk IMX8MP_CLK_ML_AHB>;
> +			clock-names = "core", "shader", "bus", "reg";
> +			power-domains = <&pgc_mlmix>;
> +		};
> +
>  		gic: interrupt-controller@38800000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x38800000 0x10000>,
Shawn Guo Nov. 27, 2023, 2:58 a.m. UTC | #2 
On Sun, Oct 22, 2023 at 11:19:10AM -0500, Adam Ford wrote:
> The NPU is based on the Vivante GC8000 and its power-domain
> is controlled my pgc_mlmix.  Since the power-domain uses
> some of these clocks, setup the clock parent and rates
> inside the power-domain, and add the NPU node.
> 
> The data sheet states the CLK_ML_AHB should be 300MHz for
> nominal, but 800MHz clock will divide down to 266 instead.
> Boards which operate in over-drive mode should update the
> clocks on their boards accordingly.  When the driver loads,
> the NPU numerates as:
> 
>  etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9a610ba4836..a18b9ba98ea2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -887,6 +887,15 @@  pgc_mlmix: power-domain@24 {
 						clocks = <&clk IMX8MP_CLK_ML_AXI>,
 							 <&clk IMX8MP_CLK_ML_AHB>,
 							 <&clk IMX8MP_CLK_NPU_ROOT>;
+						assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
+								  <&clk IMX8MP_CLK_ML_AXI>,
+								  <&clk IMX8MP_CLK_ML_AHB>;
+						assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+									 <&clk IMX8MP_SYS_PLL1_800M>,
+									 <&clk IMX8MP_SYS_PLL1_800M>;
+						assigned-clock-rates = <800000000>,
+								       <800000000>,
+								       <300000000>;
 					};
 				};
 			};
@@ -2012,6 +2021,18 @@  vpumix_blk_ctrl: blk-ctrl@38330000 {
 			interconnect-names = "g1", "g2", "vc8000e";
 		};
 
+		npu: npu@38500000 {
+			compatible = "vivante,gc";
+			reg = <0x38500000 0x200000>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
+				 <&clk IMX8MP_CLK_NPU_ROOT>,
+				 <&clk IMX8MP_CLK_ML_AXI>,
+				 <&clk IMX8MP_CLK_ML_AHB>;
+			clock-names = "core", "shader", "bus", "reg";
+			power-domains = <&pgc_mlmix>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>,