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[23.128.96.38]) by mx.google.com with ESMTPS id ep22-20020a17090ae65600b0027924ff5de3si2517609pjb.68.2023.10.19.09.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 09:56:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 2668D83BEDEB; Thu, 19 Oct 2023 09:56:52 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346320AbjJSQ4e (ORCPT + 26 others); Thu, 19 Oct 2023 12:56:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345349AbjJSQ4W (ORCPT ); Thu, 19 Oct 2023 12:56:22 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1C44912F for ; Thu, 19 Oct 2023 09:56:20 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98C552F4; Thu, 19 Oct 2023 09:57:00 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.67.150]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 783373F5A1; Thu, 19 Oct 2023 09:56:16 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, maz@kernel.org, suzuki.poulose@arm.com Cc: broonie@kernel.org, James Clark , Oliver Upton , James Morse , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Leo Yan , Alexander Shishkin , Anshuman Khandual , Rob Herring , Jintack Lim , Kristina Martsenko , Fuad Tabba , Akihiko Odaki , Joey Gouly , linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] arm64: KVM: Add interface to set guest value for TRFCR register Date: Thu, 19 Oct 2023 17:55:02 +0100 Message-Id: <20231019165510.1966367-5-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019165510.1966367-1-james.clark@arm.com> References: <20231019165510.1966367-1-james.clark@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 19 Oct 2023 09:56:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780203771787765026 X-GMAIL-MSGID: 1780203771787765026 Add an interface for the Coresight driver to use to set the value of the TRFCR register for the guest. This register controls the exclude settings for trace at different exception levels, and is used to honor the exclude_host and exclude_guest parameters from the Perf session. This will be used to later write TRFCR_EL1 on nVHE at guest switch. For VHE, the host trace is controlled by TRFCR_EL2 and thus we can write to the TRFCR_EL1 immediately. Because guest writes to the register are trapped, the value will persist and can't be modified. The settings must be copied to the vCPU before each run in the same way that PMU events are, because the per-cpu struct isn't accessible in protected mode. Signed-off-by: James Clark Reviewed-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/arm.c | 1 + arch/arm64/kvm/debug.c | 26 ++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0f0bf8e641bd..e1852102550d 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1125,6 +1125,8 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); void kvm_clr_pmu_events(u32 clr); bool kvm_set_pmuserenr(u64 val); +void kvm_etm_set_guest_trfcr(u64 trfcr_guest); +void kvm_etm_update_vcpu_events(struct kvm_vcpu *vcpu); #else static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} static inline void kvm_clr_pmu_events(u32 clr) {} @@ -1132,6 +1134,7 @@ static inline bool kvm_set_pmuserenr(u64 val) { return false; } +static inline void kvm_etm_set_guest_trfcr(u64 trfcr_guest) {} #endif void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 0f717b6a9151..e4d846f2f665 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1015,6 +1015,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) kvm_vgic_flush_hwstate(vcpu); kvm_pmu_update_vcpu_events(vcpu); + kvm_etm_update_vcpu_events(vcpu); /* * Ensure we set mode to IN_GUEST_MODE after we disable diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 20cdd40b3c42..2ab41b954512 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -23,6 +23,12 @@ static DEFINE_PER_CPU(u64, mdcr_el2); +/* + * Per CPU value for TRFCR that should be applied to any guest vcpu that may + * run on that core in the future. + */ +static DEFINE_PER_CPU(u64, guest_trfcr); + /** * save/restore_guest_debug_regs * @@ -356,3 +362,23 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); } + +void kvm_etm_set_guest_trfcr(u64 trfcr_guest) +{ + if (has_vhe()) + write_sysreg_s(trfcr_guest, SYS_TRFCR_EL12); + else + *this_cpu_ptr(&guest_trfcr) = trfcr_guest; +} +EXPORT_SYMBOL_GPL(kvm_etm_set_guest_trfcr); + +/* + * Updates the vcpu's view of the etm events for this cpu. Must be + * called before every vcpu run after disabling interrupts, to ensure + * that an interrupt cannot fire and update the structure. + */ +void kvm_etm_update_vcpu_events(struct kvm_vcpu *vcpu) +{ + if (!has_vhe() && vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRFCR)) + ctxt_sys_reg(&vcpu->arch.ctxt, TRFCR_EL1) = *this_cpu_ptr(&guest_trfcr); +}