From patchwork Wed Oct 18 23:16:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 155216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp52064vqb; Wed, 18 Oct 2023 16:18:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHc0SHrvrlR0NEtl6PGEEizdJdGFoQLmB/JxX/4WwX26uWJw5OIrk3wk5f0RCp/ZNNChuqa X-Received: by 2002:a17:90a:ea18:b0:27d:7666:d8e9 with SMTP id w24-20020a17090aea1800b0027d7666d8e9mr685929pjy.38.1697671079741; Wed, 18 Oct 2023 16:17:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697671079; cv=none; d=google.com; s=arc-20160816; b=kxle707slw16dCpgv6M8npqvZyCwBzCPjwsNMFM6pXHa7tXZ8FHdV/WYIfBqdpQA8n Qfs2248kYiqb9AbopXk0F1JKAKxJ1yss3+boZjcG7KaIByusaWyhcrSKncjMSvJdhKOw 9hkLd6lo6GKe1FMq2CvB2jb+PihT4JFRSZh64Gzfn5h5LZVixCucIRQgNz/jrVQLN4rU 5KvHRYlFIfM2u3tYjSv+4kjq6cKJ06+J+nNlHB/pnNM7N9w3Q6Et8ky0R+ijzXPDoEkI nDnczizWcpZfa+zHDX8dYLI52FfyyxH3ggAvOEKxtFqUXNLXuCoNPnSp4Fd1TUyHvqHo fxjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pMjUP9REP3On2/Y26cvGEfNx1y0JrItpp15cD28x8hQ=; fh=d9G4dsZtlI8UONIvGKwhW94hCYEPGxy6CqYeKEG646A=; b=Sqe3dpUWdaxTkX6VGMiMeC+nOc0l5gKilIVn9fqxxN9JPuWlKXwv3d5oqeA506wB7+ Vyz3fnpOYmPqb43bKSt6PMS/1jTYEzcD/PjU2KGwKCp8QvoXoV34TjriYt83rEFCUW7A 59ul5T1jwwENVgA6nXWNNpItpC0NZlmgJGynJMS8As983LiI3Wvet0T3rJH3CO6rqscJ KG0EdxYfGH8fhcDZ+HGKVs7o6ZTI31SQWbN1F5E9BnhUmEfqJrLTCRq8phEtxMosDMBB SZJLgaUYD07/irQS9fMZ1g940ulGTGf7QdDFewhlaIupM3rp8Ut026IcE2qRiRptpDf7 bGIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kSmwSHkv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id ch5-20020a17090af40500b002534f4ce2b6si871517pjb.125.2023.10.18.16.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 16:17:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kSmwSHkv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id B2A9F8225CA3; Wed, 18 Oct 2023 16:17:42 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232653AbjJRXQx (ORCPT + 24 others); Wed, 18 Oct 2023 19:16:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231963AbjJRXQ3 (ORCPT ); Wed, 18 Oct 2023 19:16:29 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35F54111; Wed, 18 Oct 2023 16:16:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697670987; x=1729206987; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ij0hJ46MmQQCzRboafmS4zwP24cbWPUtSETzKBKq7Wg=; b=kSmwSHkvki3x+jAVfMs3iuW9peLgviENw2qtJHuuubgfZ+TCt+VL40d2 /5SyEn0mDRyYJIrZGhnAeaDG1RfjveXYokqBuzN0rprpv9OIYbGz+Tn/8 G35Iz28Vg0ks0WNWbpK21TzBmQujT7LgG1LfwBFKc9Yhjzue4Q0rEEWPm FRMT65fTuiF7rxSIRsP0Dl6WQQJDLnok7jut+pSQC3IqYCZu8kBhd4LWm 08/STM200jvLtWMtX4JhBc5n5RPLYs+k20Y4u1uEX/KyFOllRISEK5GPn Fqvijiz1c4LEcr1X/1Tqxh6bckVK4IRhb002+geMFRFedfbDwIXfm1v4E A==; X-IronPort-AV: E=McAfee;i="6600,9927,10867"; a="385013049" X-IronPort-AV: E=Sophos;i="6.03,236,1694761200"; d="scan'208";a="385013049" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2023 16:16:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,236,1694761200"; d="scan'208";a="4730734" Received: from linux.intel.com ([10.54.29.200]) by fmviesa001.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2023 16:16:30 -0700 Received: from debox1-desk4.lan (unknown [10.209.71.91]) by linux.intel.com (Postfix) with ESMTP id 627AB580DD4; Wed, 18 Oct 2023 16:16:26 -0700 (PDT) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V4 14/17] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT Date: Wed, 18 Oct 2023 16:16:21 -0700 Message-Id: <20231018231624.1044633-15-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018231624.1044633-1-david.e.box@linux.intel.com> References: <20231018231624.1044633-1-david.e.box@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 18 Oct 2023 16:17:42 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780137149830360022 X-GMAIL-MSGID: 1780137149830360022 From: Xi Pardee On supported platforms, the low power mode (LPM) requirements for entering each idle substate are described in Platform Monitoring Technology (PMT) telemetry entries. Provide a function for platform code to attempt to find and read the requirements from the telemetry entries. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V4 - no change V3 - no change V2 - remove extra parens drivers/platform/x86/intel/pmc/core.h | 3 + drivers/platform/x86/intel/pmc/core_ssram.c | 135 ++++++++++++++++++++ 2 files changed, 138 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index edaa70067e41..85b6f6ae4995 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -320,6 +320,7 @@ struct pmc_reg_map { const u32 lpm_status_offset; const u32 lpm_live_status_offset; const u32 etr3_offset; + const u8 *lpm_reg_index; }; /** @@ -329,6 +330,7 @@ struct pmc_reg_map { * specific attributes */ struct pmc_info { + u32 guid; u16 devid; const struct pmc_reg_map *map; }; @@ -486,6 +488,7 @@ extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; extern const struct pmc_reg_map mtl_ioem_reg_map; extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); +extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); int pmc_core_resume_common(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index 936aa0d5f452..f007964156bc 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -24,6 +24,140 @@ #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 +/* PCH query */ +#define LPM_HEADER_OFFSET 1 +#define LPM_REG_COUNT 28 +#define LPM_MODE_OFFSET 1 + +static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map) +{ + for (; list->map; ++list) + if (list->map == map) + return list->guid; + + return 0; +} + +static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc) +{ + struct telem_endpoint *ep; + const u8 *lpm_indices; + int num_maps, mode_offset = 0; + int ret, mode, i; + int lpm_size; + u32 guid; + + lpm_indices = pmc->map->lpm_reg_index; + num_maps = pmc->map->lpm_num_maps; + lpm_size = LPM_MAX_NUM_MODES * num_maps; + + guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map); + if (!guid) + return -ENXIO; + + ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0); + if (IS_ERR(ep)) { + dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld", + PTR_ERR(ep)); + return -EPROBE_DEFER; + } + + pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev, + lpm_size * sizeof(u32), + GFP_KERNEL); + if (!pmc->lpm_req_regs) { + ret = -ENOMEM; + goto unregister_ep; + } + + /* + * PMC Low Power Mode (LPM) table + * + * In telemetry space, the LPM table contains a 4 byte header followed + * by 8 consecutive mode blocks (one for each LPM mode). Each block + * has a 4 byte header followed by a set of registers that describe the + * IP state requirements for the given mode. The IP mapping is platform + * specific but the same for each block, making for easy analysis. + * Platforms only use a subset of the space to track the requirements + * for their IPs. Callers provide the requirement registers they use as + * a list of indices. Each requirement register is associated with an + * IP map that's maintained by the caller. + * + * Header + * +----+----------------------------+----------------------------+ + * | 0 | REVISION | ENABLED MODES | + * +----+--------------+-------------+-------------+--------------+ + * + * Low Power Mode 0 Block + * +----+--------------+-------------+-------------+--------------+ + * | 1 | SUB ID | SIZE | MAJOR | MINOR | + * +----+--------------+-------------+-------------+--------------+ + * | 2 | LPM0 Requirements 0 | + * +----+---------------------------------------------------------+ + * | | ... | + * +----+---------------------------------------------------------+ + * | 29 | LPM0 Requirements 27 | + * +----+---------------------------------------------------------+ + * + * ... + * + * Low Power Mode 7 Block + * +----+--------------+-------------+-------------+--------------+ + * | | SUB ID | SIZE | MAJOR | MINOR | + * +----+--------------+-------------+-------------+--------------+ + * | 60 | LPM7 Requirements 0 | + * +----+---------------------------------------------------------+ + * | | ... | + * +----+---------------------------------------------------------+ + * | 87 | LPM7 Requirements 27 | + * +----+---------------------------------------------------------+ + * + */ + mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET; + pmc_for_each_mode(i, mode, pmcdev) { + u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps); + int m; + + for (m = 0; m < num_maps; m++) { + u8 sample_id = lpm_indices[m] + mode_offset; + + ret = pmt_telem_read32(ep, sample_id, req_offset, 1); + if (ret) { + dev_err(&pmcdev->pdev->dev, + "couldn't read Low Power Mode requirements: %d\n", ret); + devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs); + goto unregister_ep; + } + ++req_offset; + } + mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET; + } + +unregister_ep: + pmt_telem_unregister_endpoint(ep); + + return ret; +} + +int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev) +{ + int ret, i; + + if (!pmcdev->ssram_pcidev) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + if (!pmcdev->pmcs[i]) + continue; + + ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]); + if (ret) + return ret; + } + + return 0; +} + static void pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram) { @@ -215,3 +349,4 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev) return ret; } MODULE_IMPORT_NS(INTEL_VSEC); +MODULE_IMPORT_NS(INTEL_PMT_TELEMETRY);