From patchwork Wed Oct 18 10:35:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 154800 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4695137vqb; Wed, 18 Oct 2023 03:36:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEN0o7Bf5HMyo+fuySt7zMEpwfNlD0B6wd3e88Qbm99VL4cEdyhXA7Sv3UKI+jt99lttI0V X-Received: by 2002:a17:903:334c:b0:1c7:5581:f9c with SMTP id ka12-20020a170903334c00b001c755810f9cmr4829261plb.0.1697625392599; Wed, 18 Oct 2023 03:36:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697625392; cv=none; d=google.com; s=arc-20160816; b=rHjbNvR1Dl6JzmY7uzqWvbg/dLk9TipXQAzEuxPftzYY6vBDS5yH8OXBlHSp3JE+tk zzWqXfbYRLopOy/K8WddxOrGpPVnNlCYYHgfB5fbf5C6IoR18LeOQsh6HFeTHBgsBhRO 8o2WxRPvWrj3H5yGY1DwfOEUS9hi3ZzUgy6CG7wd+NR3SEBfoZLMQvdyezfsKseFupCH VpqPlWXEE8AL3Y6YU04nBsl/zWZ5wCCD+/B4T+uAQDyiODj+xGiNktt2/MvLzeRaYPG0 Xw79aYEZQKeR4QhXRHXiG24vz7Ko+ULJMlq7jxYuk5a3NhRdON0vN6whZ++gj6eoEf+T Qd7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=leHHh7J+nYXwhcMPClCWvx5ELV45fweAgYK2dMfwIQk=; fh=3eZfXf5jFPKprqHqzv1DRxQ902as4fK5jxtLLEPEL88=; b=ZmT4eFMYzx3Na9+MZoUh8EyMldrJIKahj4YmaKInvcaqWwc6floPuLxSnAkGB0c8qW 8crzLcgDutbbX1fS97A2yA4FLEdq+pH9ZOfOFiwGUcBpg90AVSSk3opnGyuMV6Ia/ySU wX5h080OqbhyEWliTHsreNE+s/Zpxi+6unk/qFBKQ95rWVGHgDH3ONG9Nbn5MyFgMro6 0SYPleUhL/oAw98FlhkGhdAui8EHxkjvEO3zp6v6k1lSr/opkgzPQsvPRUGj88nyNpyj TUs5679gC7JLrvLyDK6KwdY0/DAiKij3Ymp5nWOFzyGqlO9qsk1OFlGEKmRcYiIMBA1S pa5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="LfgFEm/f"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id li11-20020a170903294b00b001b6ae9f8bb1si3648015plb.75.2023.10.18.03.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 03:36:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="LfgFEm/f"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id A4F728108367; Wed, 18 Oct 2023 03:36:29 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235038AbjJRKgJ (ORCPT + 24 others); Wed, 18 Oct 2023 06:36:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231613AbjJRKf7 (ORCPT ); Wed, 18 Oct 2023 06:35:59 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ACD495; Wed, 18 Oct 2023 03:35:56 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9B4C866072FB; Wed, 18 Oct 2023 11:35:54 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697625355; bh=yrK40mqR2gkRIh6LcyARxcWeWdhXk/xzJHGv+Nf+PXg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LfgFEm/f04v+pcByxzoSO9i4tGJc0XpHz8JuPUicRuQOEMpANSniPFw9DdPytn67k rEztQG1EZ0kmdgTMnsozqcXbwz1WJTHbTc4ZZrGtb73/qbbschz9gIwqeph9gmU4gU XTyvGbryYM+HaZ044pjw/cEqYyiQavT9InaAKb4JAGsL6gG7tsWVq+cugq4M0HP7PE 26WLazVX2U7GzIVYFa1MK99m/mE9xVMJR8Q9J9hxlvQrGWE4dosBE4QmpsqNLYSDve BSfzBRWkCx4zmNmVxBWI1x7tYhRwgsuV3KJR2ERkIKkpEGDjOYoDQR4//FU/rbjz2e 47QO2IRZCj/mQ== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, msp@baylibre.com, amergnat@baylibre.com, yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 2/2] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes Date: Wed, 18 Oct 2023 12:35:46 +0200 Message-ID: <20231018103546.48174-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231018103546.48174-1-angelogioacchino.delregno@collabora.com> References: <20231018103546.48174-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 18 Oct 2023 03:36:29 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780089243426929376 X-GMAIL-MSGID: 1780089243426929376 The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Reviewed-by: Alexandre Mergnat Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 5c426a1c94c7..4529255376e9 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -417,15 +417,21 @@ static const char * const pwrmcu_parents[] = { static const char * const dp_parents[] = { "clk26m", - "tvdpll1_d2", "tvdpll2_d2", - "tvdpll1_d4", "tvdpll2_d4", - "tvdpll1_d8", "tvdpll2_d8", - "tvdpll1_d16", "tvdpll2_d16" }; +static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 }; + +static const char * const edp_parents[] = { + "clk26m", + "tvdpll1_d2", + "tvdpll1_d4", + "tvdpll1_d8", + "tvdpll1_d16" +}; +static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 }; static const char * const disp_pwm_parents[] = { "clk26m", @@ -957,11 +963,11 @@ static const struct mtk_mux top_mtk_muxes[] = { MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu", pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", - dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp", + dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp", - dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp", + edp_parents, edp_parents_idx, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi", dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",