diff mbox series

[v2,14/19] riscv: add ISA extension parsing for Zvfh[min]

Message ID	20231017131456.2053396-15-cleger@rivosinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Andrew Jones <ajones@ventanamicro.com>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor@kernel.org>, Samuel Ortiz <sameo@rivosinc.com> Subject: [PATCH v2 14/19] riscv: add ISA extension parsing for Zvfh[min] Date: Tue, 17 Oct 2023 15:14:51 +0200 Message-ID: <20231017131456.2053396-15-cleger@rivosinc.com> In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: report more ISA extensions through hwprobe \| [v2,00/19] riscv: report more ISA extensions through hwprobe [v2,01/19] riscv: hwprobe: factorize hwprobe ISA extension reporting [v2,02/19] riscv: add ISA extension parsing for scalar crypto [v2,03/19] riscv: hwprobe: add support for scalar crypto ISA extensions [v2,04/19] dt-bindings: riscv: add scalar crypto ISA extensions description [v2,05/19] riscv: add ISA extension parsing for vector crypto extensions [v2,06/19] riscv: hwprobe: export vector crypto ISA extensions [v2,07/19] dt-bindings: riscv: add vector crypto ISA extensions description [v2,08/19] riscv: add ISA extension parsing for Zfh/Zfhmin [v2,09/19] riscv: hwprobe: export Zfh/Zfhmin ISA extensions [v2,10/19] dt-bindings: riscv: add Zfh[min] ISA extensions description [v2,11/19] riscv: add ISA extension parsing for Zihintntl [v2,12/19] riscv: hwprobe: export Zhintntl ISA extension [v2,13/19] dt-bindings: riscv: add Zihintntl ISA extension description [v2,14/19] riscv: add ISA extension parsing for Zvfh[min] [v2,15/19] riscv: hwprobe: export Zvfh[min] ISA extensions [v2,16/19] dt-bindings: riscv: add Zvfh[min] ISA extension description [v2,17/19] riscv: add ISA extension parsing for Zfa [v2,18/19] riscv: hwprobe: export Zfa ISA extension [v2,19/19] dt-bindings: riscv: add Zfa ISA extension description

Commit Message

Clément Léger Oct. 17, 2023, 1:14 p.m. UTC

  Add parsing for Zvfh[min] ISA extension[1] which were ratified in
june 2023 around commit e2ccd0548d6c ("Remove draft warnings from
Zvfh[min]") in riscv-v-spec[2].

Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
Link: https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 2 ++
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 4 insertions(+)

Comments

Evan Green Oct. 18, 2023, 5:28 p.m. UTC | #1

On Tue, Oct 17, 2023 at 6:15 AM Clément Léger <cleger@rivosinc.com> wrote:
>
> Add parsing for Zvfh[min] ISA extension[1] which were ratified in
> june 2023 around commit e2ccd0548d6c ("Remove draft warnings from
> Zvfh[min]") in riscv-v-spec[2].
>
> Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [1]
> Link: https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c [2]
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Evan Green <evan@rivosinc.com>

diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index a9aea62b6c6f..d9fb782f198d 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -82,6 +82,8 @@ 
 #define RISCV_ISA_EXT_ZFH		64
 #define RISCV_ISA_EXT_ZFHMIN		65
 #define RISCV_ISA_EXT_ZIHINTNTL		66
+#define RISCV_ISA_EXT_ZVFH		67
+#define RISCV_ISA_EXT_ZVFHMIN		68
 
 #define RISCV_ISA_EXT_MAX		128
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 0a74b2cdcacf..c70885f5014b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -266,6 +266,8 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
 	__RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
 	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
+	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
 	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
 	__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
 	__RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),