diff mbox series

[v2,12/19] riscv: hwprobe: export Zhintntl ISA extension

Message ID	20231017131456.2053396-13-cleger@rivosinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Andrew Jones <ajones@ventanamicro.com>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor@kernel.org>, Samuel Ortiz <sameo@rivosinc.com> Subject: [PATCH v2 12/19] riscv: hwprobe: export Zhintntl ISA extension Date: Tue, 17 Oct 2023 15:14:49 +0200 Message-ID: <20231017131456.2053396-13-cleger@rivosinc.com> In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: report more ISA extensions through hwprobe \| [v2,00/19] riscv: report more ISA extensions through hwprobe [v2,01/19] riscv: hwprobe: factorize hwprobe ISA extension reporting [v2,02/19] riscv: add ISA extension parsing for scalar crypto [v2,03/19] riscv: hwprobe: add support for scalar crypto ISA extensions [v2,04/19] dt-bindings: riscv: add scalar crypto ISA extensions description [v2,05/19] riscv: add ISA extension parsing for vector crypto extensions [v2,06/19] riscv: hwprobe: export vector crypto ISA extensions [v2,07/19] dt-bindings: riscv: add vector crypto ISA extensions description [v2,08/19] riscv: add ISA extension parsing for Zfh/Zfhmin [v2,09/19] riscv: hwprobe: export Zfh/Zfhmin ISA extensions [v2,10/19] dt-bindings: riscv: add Zfh[min] ISA extensions description [v2,11/19] riscv: add ISA extension parsing for Zihintntl [v2,12/19] riscv: hwprobe: export Zhintntl ISA extension [v2,13/19] dt-bindings: riscv: add Zihintntl ISA extension description [v2,14/19] riscv: add ISA extension parsing for Zvfh[min] [v2,15/19] riscv: hwprobe: export Zvfh[min] ISA extensions [v2,16/19] dt-bindings: riscv: add Zvfh[min] ISA extension description [v2,17/19] riscv: add ISA extension parsing for Zfa [v2,18/19] riscv: hwprobe: export Zfa ISA extension [v2,19/19] dt-bindings: riscv: add Zfa ISA extension description

Commit Message

Clément Léger Oct. 17, 2023, 1:14 p.m. UTC

  Export Zihintntl extension[1] through hwprobe.

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 Documentation/riscv/hwprobe.rst       | 3 +++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_riscv.c         | 1 +
 3 files changed, 5 insertions(+)

Comments

Evan Green Oct. 18, 2023, 5:28 p.m. UTC | #1

On Tue, Oct 17, 2023 at 6:15 AM Clément Léger <cleger@rivosinc.com> wrote:
>
> Export Zihintntl extension[1] through hwprobe.
>
> Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Evan Green <evan@rivosinc.com>

diff mbox series

Patch

diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 35aedfff5049..9c909e0d5316 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -143,6 +143,9 @@  The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
        supported as defined in the RISC-V ISA manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
+       is supported as defined in the RISC-V ISA manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 390805c49674..dc4eaa978ad1 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -51,6 +51,7 @@  struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZVKT		(1 << 25)
 #define		RISCV_HWPROBE_EXT_ZFH		(1 << 26)
 #define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 27)
+#define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 28)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 4cca8b982a7a..84daaf6ed4a1 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -172,6 +172,7 @@  static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		CHECK_ISA_EXT(ZKSED);
 		CHECK_ISA_EXT(ZKSH);
 		CHECK_ISA_EXT(ZKT);
+		CHECK_ISA_EXT(ZIHINTNTL);
 
 		if (has_vector()) {
 			CHECK_ISA_EXT(ZVBB);